update=lun 15 apr 2019 17:25:36 CEST last_client=kicad [general] version=1 [pcbnew] version=1 PageLayoutDescrFile= LastNetListRead= CopperLayerCount=2 BoardThickness=1.6 AllowMicroVias=0 AllowBlindVias=0 RequireCourtyardDefinitions=0 ProhibitOverlappingCourtyards=1 MinTrackWidth=0.2 MinViaDiameter=0.4 MinViaDrill=0.3 MinMicroViaDiameter=0.2 MinMicroViaDrill=0.09999999999999999 MinHoleToHole=0.25 TrackWidth1=0.75 ViaDiameter1=1.6 ViaDrill1=0.8 dPairWidth1=0.2 dPairGap1=0.25 dPairViaGap1=0.25 SilkLineWidth=0.12 SilkTextSizeV=1 SilkTextSizeH=1 SilkTextSizeThickness=0.15 SilkTextItalic=0 SilkTextUpright=1 CopperLineWidth=0.2 CopperTextSizeV=1.5 CopperTextSizeH=1.5 CopperTextThickness=0.3 CopperTextItalic=0 CopperTextUpright=1 EdgeCutLineWidth=0.05 CourtyardLineWidth=0.05 OthersLineWidth=0.12 OthersTextSizeV=1 OthersTextSizeH=1 OthersTextSizeThickness=0.15 OthersTextItalic=0 OthersTextUpright=1 SolderMaskClearance=0.051 SolderMaskMinWidth=0.25 SolderPasteClearance=0 SolderPasteRatio=-0 [pcbnew/Netclasses] [pcbnew/Netclasses/1] Name=Power Clearance=0.4 TrackWidth=1.5 ViaDiameter=1.6 ViaDrill=0.8 uViaDiameter=0.3 uViaDrill=0.1 dPairWidth=0.2 dPairGap=0.25 dPairViaGap=0.25 [schematic_editor] version=1 PageLayoutDescrFile= PlotDirectoryName=plots/ SubpartIdSeparator=0 SubpartFirstId=65 NetFmtName= SpiceAjustPassiveValues=0 LabSize=50 ERC_TestSimilarLabels=1