#ifndef SYSTEM_H_INCLUDED
#define SYSTEM_H_INCLUDED
#include <stdint.h>

/* System specific: PLL with 8 MHz external oscillator, CPU at 168MHz */
#define CPU_FREQ (48000000)
#define PLL_FULL_MASK (0x7F037FFF)

/* STM32 specific defines */
#define APB1_CLOCK_ER           (*(volatile uint32_t *)(0x40023840))
#define APB1_CLOCK_RST          (*(volatile uint32_t *)(0x40023820))
#define TIM2_APB1_CLOCK_ER_VAL 	(1 << 0)
#define PWR_APB1_CLOCK_ER_VAL   (1 << 28)

#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
#define APB2_CLOCK_RST          (*(volatile uint32_t *)(0x40023824))
#define SYSCFG_APB2_CLOCK_ER (1 << 14)

/* SCB for sleep configuration */
#define SCB_SCR (*(volatile uint32_t *)(0xE000ED10))
#define SCB_SCR_SEVONPEND	(1 << 4)
#define SCB_SCR_SLEEPDEEP		(1 << 2)
#define SCB_SCR_SLEEPONEXIT (1 << 1)

/* Assembly helpers */
#define DMB() __asm__ volatile ("dmb")
#define WFI() __asm__ volatile ("wfi")
#define WFE() __asm__ volatile ("wfe")
#define SEV() __asm__ volatile ("sev")

/* Master clock setting */
void clock_pll_on(int powersave);
void clock_pll_off(void);


/* NVIC */
/* NVIC ISER Base register (Cortex-M) */
#define NVIC_EXTI0_IRQN          (6)
#define NVIC_EXTI1_IRQN          (7)
#define NVIC_EXTI2_IRQN          (8)
#define NVIC_EXTI3_IRQN          (9)
#define NVIC_EXTI4_IRQN          (10)
#define NVIC_TIM2_IRQN           (28)
#define NVIC_ISER_BASE (0xE000E100)
#define NVIC_ICER_BASE (0xE000E180)
#define NVIC_ICPR_BASE (0xE000E280)
#define NVIC_IPRI_BASE (0xE000E400)

static inline void nvic_irq_enable(uint8_t n)
{
    int i = n / 32;
    volatile uint32_t *nvic_iser = ((volatile uint32_t *)(NVIC_ISER_BASE + 4 * i));
    *nvic_iser |= (1 << (n % 32));
}

static inline void nvic_irq_disable(uint8_t n)
{
    int i = n / 32;
    volatile uint32_t *nvic_icer = ((volatile uint32_t *)(NVIC_ICER_BASE + 4 * i));
    *nvic_icer |= (1 << (n % 32));
}

static inline void nvic_irq_setprio(uint8_t n, uint8_t prio)
{
    volatile uint8_t *nvic_ipri = ((volatile uint8_t *)(NVIC_IPRI_BASE + n));
    *nvic_ipri = prio;
}


static inline void nvic_irq_clear(uint8_t n)
{
    int i = n / 32;
    volatile uint8_t *nvic_icpr = ((volatile uint8_t *)(NVIC_ICPR_BASE + 4 * i));
    *nvic_icpr = (1 << (n % 32));
}




#endif