209 lines
5.9 KiB
C
209 lines
5.9 KiB
C
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#ifndef SYSTEM_H_INCLUDED
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#define SYSTEM_H_INCLUDED
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/* System specific: PLL with 8 MHz external oscillator, CPU at 168MHz */
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#define CPU_FREQ (48000000)
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#define PLL_FULL_MASK (0x7F037FFF)
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/* STM32 specific defines */
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#define APB1_CLOCK_ER (*(volatile uint32_t *)(0x40023840))
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#define APB1_CLOCK_RST (*(volatile uint32_t *)(0x40023820))
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#define TIM2_APB1_CLOCK_ER_VAL (1 << 0)
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#define PWR_APB1_CLOCK_ER_VAL (1 << 28)
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
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#define APB2_CLOCK_RST (*(volatile uint32_t *)(0x40023824))
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#define SYSCFG_APB2_CLOCK_ER (1 << 14)
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#define RCC_BACKUP (*(volatile uint32_t *)(0x40023870))
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#define RCC_BACKUP_RESET (1 << 16)
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#define RCC_BACKUP_RTCEN (1 << 15)
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#define RCC_BACKUP_RTCSEL_SHIFT 8
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#define RCC_BACKUP_RTCSEL_MASK 0x3
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#define RCC_BACKUP_RTCSEL_NONE 0
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#define RCC_BACKUP_RTCSEL_LSE 1
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#define RCC_BACKUP_RTCSEL_LSI 2
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#define RCC_BACKUP_RTCSEL_HSE 3
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#define RCC_BACKUP_LSEMOD (1 << 3)
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#define RCC_BACKUP_LSEBYP (1 << 2)
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#define RCC_BACKUP_LSERDY (1 << 1)
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#define RCC_BACKUP_LSEON (1 << 0)
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#define RCC_CSR_LSION (1 << 0)
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#define RCC_CSR_LSIRDY (1 << 1)
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/* EXTI */
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#define EXTI_CR_BASE (0x40013808)
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#define EXTI_CR0 (*(volatile uint32_t *)(EXTI_CR_BASE + 0x00))
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#define EXTI_CR_EXTI0_MASK (0xFFFF)
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#define EXTI_IMR (*(volatile uint32_t *)(EXTI_BASE + 0x00))
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#define EXTI_EMR (*(volatile uint32_t *)(EXTI_BASE + 0x04))
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#define EXTI_RTSR (*(volatile uint32_t *)(EXTI_BASE + 0x08))
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#define EXTI_FTSR (*(volatile uint32_t *)(EXTI_BASE + 0x0c))
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#define EXTI_SWIER (*(volatile uint32_t *)(EXTI_BASE + 0x10))
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#define EXTI_PR (*(volatile uint32_t *)(EXTI_BASE + 0x14))
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/* SCB for sleep configuration */
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#define SCB_SCR (*(volatile uint32_t *)(0xE000ED10))
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#define SCB_SCR_SEVONPEND (1 << 4)
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#define SCB_SCR_SLEEPDEEP (1 << 2)
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#define SCB_SCR_SLEEPONEXIT (1 << 1)
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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#define WFI() __asm__ volatile ("wfi")
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#define WFE() __asm__ volatile ("wfe")
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#define SEV() __asm__ volatile ("sev")
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/* Master clock setting */
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void clock_pll_on(int powersave);
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void clock_pll_off(void);
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/* NVIC */
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/* NVIC ISER Base register (Cortex-M) */
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#define NVIC_RTC_IRQ (3)
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#define NVIC_EXTI0_IRQN (6)
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#define NVIC_TIM2_IRQN (28)
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#define NVIC_ISER_BASE (0xE000E100)
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#define NVIC_ICER_BASE (0xE000E180)
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#define NVIC_ICPR_BASE (0xE000E280)
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#define NVIC_IPRI_BASE (0xE000E400)
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static inline void nvic_irq_enable(uint8_t n)
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{
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int i = n / 32;
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volatile uint32_t *nvic_iser = ((volatile uint32_t *)(NVIC_ISER_BASE + 4 * i));
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*nvic_iser |= (1 << (n % 32));
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}
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static inline void nvic_irq_disable(uint8_t n)
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{
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int i = n / 32;
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volatile uint32_t *nvic_icer = ((volatile uint32_t *)(NVIC_ICER_BASE + 4 * i));
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*nvic_icer |= (1 << (n % 32));
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}
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static inline void nvic_irq_setprio(uint8_t n, uint8_t prio)
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{
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volatile uint8_t *nvic_ipri = ((volatile uint8_t *)(NVIC_IPRI_BASE + n));
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*nvic_ipri = prio;
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}
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static inline void nvic_irq_clear(uint8_t n)
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{
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int i = n / 32;
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volatile uint8_t *nvic_icpr = ((volatile uint8_t *)(NVIC_ICPR_BASE + 4 * i));
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*nvic_icpr = (1 << (n % 32));
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}
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/*** FLASH ***/
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#define FLASH_BASE (0x40023C00)
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
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#define FLASH_ACR_ENABLE_DATA_CACHE (1 << 10)
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#define FLASH_ACR_ENABLE_INST_CACHE (1 << 9)
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/*** RCC ***/
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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#define RCC_CFGR_SW_HSI 0x0
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#define RCC_CFGR_SW_HSE 0x1
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#define RCC_CFGR_SW_PLL 0x2
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#define RCC_PLLCFGR_PLLSRC (1 << 22)
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#define RCC_PRESCALER_DIV_NONE 0
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#define RCC_PRESCALER_DIV_2 8
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#define RCC_PRESCALER_DIV_4 9
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/* POWER CONTROL REGISTER */
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#define POW_BASE (0x40007000)
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#define POW_CR (*(volatile uint32_t *)(POW_BASE + 0x00))
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#define POW_SCR (*(volatile uint32_t *)(POW_BASE + 0x04))
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#define POW_CR_VOS (1 << 14)
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#define POW_CR_FPDS (1 << 9)
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#define POW_CR_DPB (1 << 8)
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#define POW_CR_CSBF (1 << 3)
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#define POW_CR_CWUF (1 << 2)
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#define POW_CR_PDDS (1 << 1)
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#define POW_CR_LPDS (1 << 0)
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#define POW_SCR_BRE (1 << 9)
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#define POW_SCR_EWUP (1 << 4)
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#define POW_SCR_BRR (1 << 3)
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#define POW_SCR_WUF (1 << 0)
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#if (CPU_FREQ == 168000000)
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# define PLLM 8
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# define PLLN 336
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# define PLLP 2
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# define PLLQ 7
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# define PLLR 0
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# define POWER_SAVE 1
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# define HPRE RCC_PRESCALER_DIV_NONE
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# define PPRE1 RCC_PRESCALER_DIV_4
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# define PPRE2 RCC_PRESCALER_DIV_2
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# define FLASH_WAITSTATES 5
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#elif (CPU_FREQ == 120000000)
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# define PLLM 8
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# define PLLN 240
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# define PLLP 2
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# define PLLQ 5
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# define PLLR 0
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# define HPRE RCC_PRESCALER_DIV_NONE
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# define PPRE1 RCC_PRESCALER_DIV_4
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# define PPRE2 RCC_PRESCALER_DIV_2
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# define FLASH_WAITSTATES 3
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#elif (CPU_FREQ == 100000000)
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# define PLLM 8
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# define PLLN 192
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# define PLLP 2
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# define PLLQ 4
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# define PLLR 0
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# define POWER_SAVE 1
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# define HPRE RCC_PRESCALER_DIV_NONE
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# define PPRE1 RCC_PRESCALER_DIV_2
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# define PPRE2 RCC_PRESCALER_DIV_NONE
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# define FLASH_WAITSTATES 2
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#elif (CPU_FREQ == 84000000)
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# define PLLM 8
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# define PLLN 336
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# define PLLP 4
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# define PLLQ 7
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# define PLLR 0
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# define HPRE RCC_PRESCALER_DIV_NONE
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# define PPRE1 RCC_PRESCALER_DIV_2
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# define PPRE2 RCC_PRESCALER_DIV_NONE
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# define FLASH_WAITSTATES 2
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#elif (CPU_FREQ == 48000000)
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# define PLLM 8
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# define PLLN 96
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# define PLLP 2
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# define PLLQ 2
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# define PLLR 0
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# define POWER_SAVE 1
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# define HPRE RCC_PRESCALER_DIV_NONE
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# define PPRE1 RCC_PRESCALER_DIV_4
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# define PPRE2 RCC_PRESCALER_DIV_2
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# define FLASH_WAITSTATES 3
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#else
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# error "Please select a valid CPU_FREQ in system.h"
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#endif
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#endif
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