152 lines
4.1 KiB
C
152 lines
4.1 KiB
C
/* spi_drv.h
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*
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* Driver for the SPI back-end of the SPI_FLASH module.
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*
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* Example implementation for stm32F4, using SPI1.
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*
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* Pinout: see spi_drv_stm32f4.h
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*
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*
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* this is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* this software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include "spi_drv.h"
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#include "spi_drv_stm32f4.h"
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void spi_cs_off(void)
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{
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GPIOA_BSRR |= (1 << SPI_FLASH_PIN);
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while(!(GPIOA_ODR & (1 << SPI_FLASH_PIN)))
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;
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}
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void spi_cs_on(void)
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{
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GPIOA_BSRR |= (1 << (SPI_FLASH_PIN + 16));
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while(GPIOA_ODR & (1 << SPI_FLASH_PIN))
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;
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}
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static void spi_flash_pin_setup(void)
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{
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uint32_t reg;
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AHB1_CLOCK_ER |= GPIOA_AHB1_CLOCK_ER;
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reg = GPIOA_MODE & ~ (0x03 << (SPI_FLASH_PIN * 2));
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GPIOA_MODE = reg | (1 << (SPI_FLASH_PIN * 2));
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reg = GPIOA_PUPD & ~(0x03 << (SPI_FLASH_PIN * 2));
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GPIOA_PUPD = reg | (0x01 << (SPI_FLASH_PIN * 2));
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reg = GPIOA_OSPD & ~(0x03 << (SPI_FLASH_PIN * 2));
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GPIOA_OSPD |= (0x03 << (SPI_FLASH_PIN * 2));
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}
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static void spi1_pins_setup(void)
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{
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uint32_t reg;
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AHB1_CLOCK_ER |= GPIOA_AHB1_CLOCK_ER;
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/* Set mode = AF */
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reg = GPIOA_MODE & ~ (0x03 << (SPI1_CLOCK_PIN * 2));
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GPIOA_MODE = reg | (2 << (SPI1_CLOCK_PIN * 2));
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reg = GPIOA_MODE & ~ (0x03 << (SPI1_MOSI_PIN * 2));
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GPIOA_MODE = reg | (2 << (SPI1_MOSI_PIN * 2));
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reg = GPIOA_MODE & ~ (0x03 << (SPI1_MISO_PIN * 2));
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GPIOA_MODE = reg | (2 << (SPI1_MISO_PIN * 2));
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/* Alternate function: use low pins (5,6,7) */
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reg = GPIOA_AFL & ~(0xf << ((SPI1_CLOCK_PIN) * 4));
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GPIOA_AFL = reg | (SPI1_PIN_AF << ((SPI1_CLOCK_PIN) * 4));
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reg = GPIOA_AFL & ~(0xf << ((SPI1_MOSI_PIN) * 4));
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GPIOA_AFL = reg | (SPI1_PIN_AF << ((SPI1_MOSI_PIN) * 4));
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reg = GPIOA_AFL & ~(0xf << ((SPI1_MISO_PIN) * 4));
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GPIOA_AFL = reg | (SPI1_PIN_AF << ((SPI1_MISO_PIN) * 4));
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}
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static void spi_pins_release(void)
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{
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uint32_t reg;
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/* Set mode = 0 */
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GPIOA_MODE &= ~ (0x03 << (SPI1_CLOCK_PIN * 2));
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GPIOA_MODE &= ~ (0x03 << (SPI1_MOSI_PIN * 2));
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GPIOA_MODE &= ~ (0x03 << (SPI1_MISO_PIN * 2));
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/* Alternate function clear */
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GPIOA_AFL &= ~(0xf << ((SPI1_CLOCK_PIN) * 4));
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GPIOA_AFL &= ~(0xf << ((SPI1_MOSI_PIN) * 4));
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GPIOA_AFL &= ~(0xf << ((SPI1_MISO_PIN) * 4));
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/* Floating */
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GPIOA_PUPD &= ~ (0x03 << (SPI1_CLOCK_PIN * 2));
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GPIOA_PUPD &= ~ (0x03 << (SPI1_MOSI_PIN * 2));
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GPIOA_PUPD &= ~ (0x03 << (SPI1_MISO_PIN * 2));
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/* Release CS */
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GPIOA_MODE &= ~ (0x03 << (SPI_FLASH_PIN * 2));
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GPIOA_PUPD &= ~ (0x03 << (SPI_FLASH_PIN * 2));
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/* Disable GPIOA clock */
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AHB1_CLOCK_ER &= ~(GPIOA_AHB1_CLOCK_ER);
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}
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static void spi1_reset(void)
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{
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APB2_CLOCK_RST |= SPI1_APB2_CLOCK_ER_VAL;
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APB2_CLOCK_RST &= ~SPI1_APB2_CLOCK_ER_VAL;
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}
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uint8_t spi_read(void)
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{
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volatile uint32_t reg;
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do {
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reg = SPI1_SR;
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} while(!(reg & SPI_SR_RX_NOTEMPTY));
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return (uint8_t)SPI1_DR;
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}
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void spi_write(const char byte)
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{
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int i;
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volatile uint32_t reg;
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do {
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reg = SPI1_SR;
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} while ((reg & SPI_SR_TX_EMPTY) == 0);
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SPI1_DR = byte;
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do {
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reg = SPI1_SR;
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} while ((reg & SPI_SR_TX_EMPTY) == 0);
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}
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void spi_init(int polarity, int phase)
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{
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spi1_pins_setup();
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spi_flash_pin_setup();
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APB2_CLOCK_ER |= SPI1_APB2_CLOCK_ER_VAL;
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spi1_reset();
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SPI1_CR1 = SPI_CR1_MASTER | (2 << 3) | (polarity << 1) | (phase << 0);
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SPI1_CR2 |= SPI_CR2_SSOE;
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SPI1_CR1 |= SPI_CR1_SPI_EN;
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}
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void spi_release(void)
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{
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spi1_reset();
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SPI1_CR2 &= ~SPI_CR2_SSOE;
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SPI1_CR1 = 0;
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spi_pins_release();
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}
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