151 lines
3.8 KiB
C
151 lines
3.8 KiB
C
/*
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* This is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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* this software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software. If not, see <http://www.gnu.org/licenses/>.
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*
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* Author: Daniele Lacamera
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*
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*
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*/
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#include <stdint.h>
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#include "system.h"
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#include <unicore-mx/stm32/gpio.h>
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#include <unicore-mx/stm32/rcc.h>
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#include <unicore-mx/cm3/nvic.h>
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extern uint32_t cpu_freq;
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static void flash_set_waitstates(int waitstates)
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{
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FLASH_ACR |= waitstates | FLASH_ACR_ENABLE_DATA_CACHE | FLASH_ACR_ENABLE_INST_CACHE;
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}
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void clock_pll_off(void)
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{
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uint32_t reg32;
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/* Enable internal high-speed oscillator. */
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RCC_CR |= RCC_CR_HSION;
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DMB();
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while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
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/* Select HSI as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSI);
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DMB();
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/* Turn off PLL */
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RCC_CR &= ~RCC_CR_PLLON;
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DMB();
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}
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void clock_pll_on(int powersave)
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{
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uint32_t reg32;
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uint32_t plln, pllm, pllq, pllp, pllr, hpre, ppre1, ppre2, flash_waitstates;
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/* Enable Power controller */
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APB1_CLOCK_ER |= PWR_APB1_CLOCK_ER_VAL;
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/* Select clock parameters */
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cpu_freq = 100000000;
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pllm = 12;
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plln = 192;
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pllp = 2;
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pllq = 4;
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pllr = 0;
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hpre = RCC_PRESCALER_DIV_NONE;
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ppre1 = RCC_PRESCALER_DIV_2;
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ppre2 = RCC_PRESCALER_DIV_NONE;
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flash_waitstates = 2;
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flash_set_waitstates(flash_waitstates);
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/* Enable internal high-speed oscillator. */
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RCC_CR |= RCC_CR_HSION;
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DMB();
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while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
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/* Select HSI as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSI);
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DMB();
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/* Enable external high-speed oscillator 12MHz. */
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RCC_CR |= RCC_CR_HSEON;
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DMB();
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while ((RCC_CR & RCC_CR_HSERDY) == 0) {};
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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*/
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reg32 = RCC_CFGR;
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reg32 &= ~(0xF0);
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RCC_CFGR = (reg32 | (hpre << 4));
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DMB();
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reg32 = RCC_CFGR;
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reg32 &= ~(0x1C00);
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RCC_CFGR = (reg32 | (ppre1 << 10));
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DMB();
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reg32 = RCC_CFGR;
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reg32 &= ~(0x07 << 13);
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RCC_CFGR = (reg32 | (ppre2 << 13));
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DMB();
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/* Set PLL config */
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(PLL_FULL_MASK);
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RCC_PLLCFGR = reg32 | RCC_PLLCFGR_PLLSRC | pllm |
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(plln << 6) | (((pllp >> 1) - 1) << 16) |
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(pllq << 24);
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DMB();
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/* Enable power-save mode if selected */
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POW_CR |= (POW_CR_VOS);
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/* Enable PLL oscillator and wait for it to stabilize. */
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RCC_CR |= RCC_CR_PLLON;
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DMB();
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while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
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/* Select PLL as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
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DMB();
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/* Wait for PLL clock to be selected. */
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
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/* Disable internal high-speed oscillator. */
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RCC_CR &= ~RCC_CR_HSION;
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}
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void *__attribute__((weak)) memcpy(void *d, void *s, uint32_t len)
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{
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uint32_t *src, *dst;
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uint8_t *sb, *db;
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src = s;
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dst = d;
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while(len > 3) {
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*(dst++) = *(src++);
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len -= 4;
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}
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sb = (uint8_t *)src;
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db = (uint8_t *)dst;
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while(len > 0) {
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*(db++) = *(sb++);
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len--;
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}
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return d;
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}
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