SSP0_CR0,0,4,DSS,Data Size Select,0,rw
SSP0_CR0,4,2,FRF,Frame Format,0,rw
SSP0_CR0,6,1,CPOL,Clock Out Polarity,0,rw
SSP0_CR0,7,1,CPHA,Clock Out Phase,0,rw
SSP0_CR0,8,8,SCR,Serial Clock Rate,0,rw
SSP1_CR0,0,4,DSS,Data Size Select,0,rw
SSP1_CR0,4,2,FRF,Frame Format,0,rw
SSP1_CR0,6,1,CPOL,Clock Out Polarity,0,rw
SSP1_CR0,7,1,CPHA,Clock Out Phase,0,rw
SSP1_CR0,8,8,SCR,Serial Clock Rate,0,rw
SSP0_CR1,0,1,LBM,Loop Back Mode,0,rw
SSP0_CR1,1,1,SSE,SSP Enable,0,rw
SSP0_CR1,2,1,MS,Master/Slave Mode,0,rw
SSP0_CR1,3,1,SOD,Slave Output Disable,0,rw
SSP1_CR1,1,1,SSE,SSP Enable,0,rw
SSP1_CR1,2,1,MS,Master/Slave Mode,0,rw
SSP1_CR1,3,1,SOD,Slave Output Disable,0,rw
SSP0_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
SSP1_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
SSP0_SR,0,1,TFE,Transmit FIFO Empty,1,r
SSP0_SR,1,1,TNF,Transmit FIFO Not Full,1,r
SSP0_SR,2,1,RNE,Receive FIFO Not Empty,0,r
SSP0_SR,3,1,RFF,Receive FIFO Full,0,r
SSP0_SR,4,1,BSY,Busy.,0,r
SSP1_SR,0,1,TFE,Transmit FIFO Empty,1,r
SSP1_SR,1,1,TNF,Transmit FIFO Not Full,1,r
SSP1_SR,2,1,RNE,Receive FIFO Not Empty,0,r
SSP1_SR,3,1,RFF,Receive FIFO Full,0,r
SSP1_SR,4,1,BSY,Busy.,0,r
SSP0_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
SSP1_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
SSP0_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
SSP0_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
SSP0_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
SSP0_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
SSP1_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
SSP1_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
SSP1_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
SSP1_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
SSP0_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
SSP0_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
SSP0_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
SSP0_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
SSP1_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
SSP1_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
SSP1_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
SSP1_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
SSP0_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
SSP0_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
SSP0_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
SSP0_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
SSP1_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
SSP1_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
SSP1_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
SSP1_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
SSP0_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
SSP0_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
SSP1_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
SSP1_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
SSP0_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
SSP0_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
SSP1_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
SSP1_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
