SGPIO_OUT_MUX_CFG0,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG0,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG1,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG1,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG2,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG2,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG3,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG3,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG4,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG4,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG5,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG5,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG6,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG6,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG7,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG7,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG8,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG8,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG9,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG9,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG10,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG10,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG11,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG11,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG12,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG12,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG13,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG13,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG14,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG14,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG15,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG15,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_MUX_CFG0,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG0,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG0,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG0,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG0,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG0,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG0,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG0,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG1,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG1,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG1,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG1,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG1,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG1,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG1,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG1,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG2,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG2,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG2,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG2,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG2,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG2,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG2,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG2,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG3,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG3,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG3,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG3,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG3,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG3,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG3,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG3,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG4,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG4,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG4,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG4,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG4,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG4,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG4,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG4,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG5,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG5,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG5,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG5,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG5,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG5,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG5,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG5,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG6,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG6,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG6,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG6,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG6,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG6,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG6,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG6,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG7,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG7,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG7,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG7,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG7,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG7,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG7,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG7,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG8,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG8,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG8,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG8,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG8,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG8,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG8,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG8,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG9,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG9,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG9,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG9,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG9,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG9,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG9,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG9,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG10,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG10,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG10,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG10,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG10,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG10,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG10,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG10,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG11,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG11,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG11,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG11,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG11,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG11,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG11,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG11,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG12,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG12,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG12,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG12,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG12,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG12,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG12,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG12,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG13,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG13,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG13,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG13,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG13,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG13,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG13,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG13,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG14,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG14,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG14,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG14,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG14,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG14,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG14,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG14,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG15,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG15,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG15,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG15,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG15,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG15,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG15,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG15,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_SLICE_MUX_CFG0,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG0,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG0,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG0,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG0,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG0,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG0,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG1,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG1,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG1,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG1,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG1,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG1,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG1,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG2,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG2,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG2,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG2,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG2,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG2,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG2,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG3,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG3,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG3,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG3,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG3,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG3,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG3,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG4,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG4,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG4,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG4,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG4,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG4,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG4,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG5,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG5,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG5,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG5,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG5,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG5,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG5,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG6,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG6,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG6,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG6,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG6,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG6,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG6,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG7,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG7,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG7,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG7,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG7,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG7,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG7,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG8,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG8,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG8,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG8,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG8,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG8,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG8,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG9,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG9,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG9,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG9,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG9,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG9,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG9,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG10,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG10,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG10,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG10,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG10,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG10,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG10,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG11,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG11,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG11,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG11,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG11,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG11,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG11,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG12,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG12,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG12,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG12,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG12,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG12,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG12,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG13,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG13,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG13,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG13,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG13,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG13,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG13,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG14,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG14,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG14,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG14,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG14,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG14,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG14,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG15,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG15,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG15,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG15,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG15,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG15,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG15,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_POS0,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS0,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS1,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS1,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS2,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS2,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS3,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS3,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS4,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS4,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS5,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS5,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS6,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS6,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS7,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS7,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS8,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS8,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS9,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS9,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS10,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS10,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS11,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS11,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS12,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS12,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS13,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS13,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS14,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS14,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS15,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS15,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
