RESET_CTRL0,0,1,CORE_RST,Writing a one activates the reset,0,w
RESET_CTRL0,1,1,PERIPH_RST,Writing a one activates the reset,0,w
RESET_CTRL0,2,1,MASTER_RST,Writing a one activates the reset,0,w
RESET_CTRL0,4,1,WWDT_RST,Writing a one to this bit has no effect,0,
RESET_CTRL0,5,1,CREG_RST,Writing a one to this bit has no effect,0,
RESET_CTRL0,8,1,BUS_RST,Writing a one activates the reset,0,w
RESET_CTRL0,9,1,SCU_RST,Writing a one activates the reset,0,w
RESET_CTRL0,13,1,M4_RST,Writing a one activates the reset,0,w
RESET_CTRL0,16,1,LCD_RST,Writing a one activates the reset,0,w
RESET_CTRL0,17,1,USB0_RST,Writing a one activates the reset,0,w
RESET_CTRL0,18,1,USB1_RST,Writing a one activates the reset,0,w
RESET_CTRL0,19,1,DMA_RST,Writing a one activates the reset,0,w
RESET_CTRL0,20,1,SDIO_RST,Writing a one activates the reset,0,w
RESET_CTRL0,21,1,EMC_RST,Writing a one activates the reset,0,w
RESET_CTRL0,22,1,ETHERNET_RST,Writing a one activates the reset,0,w
RESET_CTRL0,25,1,FLASHA_RST,Writing a one activates the reset,0,w
RESET_CTRL0,27,1,EEPROM_RST,Writing a one activates the reset,0,w
RESET_CTRL0,28,1,GPIO_RST,Writing a one activates the reset,0,w
RESET_CTRL0,29,1,FLASHB_RST,Writing a one activates the reset,0,w
RESET_CTRL1,0,1,TIMER0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,1,1,TIMER1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,2,1,TIMER2_RST,Writing a one activates the reset,0,w
RESET_CTRL1,3,1,TIMER3_RST,Writing a one activates the reset,0,w
RESET_CTRL1,4,1,RTIMER_RST,Writing a one activates the reset,0,w
RESET_CTRL1,5,1,SCT_RST,Writing a one activates the reset,0,w
RESET_CTRL1,6,1,MOTOCONPWM_RST,Writing a one activates the reset,0,w
RESET_CTRL1,7,1,QEI_RST,Writing a one activates the reset,0,w
RESET_CTRL1,8,1,ADC0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,9,1,ADC1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,10,1,DAC_RST,Writing a one activates the reset,0,w
RESET_CTRL1,12,1,UART0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,13,1,UART1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,14,1,UART2_RST,Writing a one activates the reset,0,w
RESET_CTRL1,15,1,UART3_RST,Writing a one activates the reset,0,w
RESET_CTRL1,16,1,I2C0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,17,1,I2C1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,18,1,SSP0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,19,1,SSP1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,20,1,I2S_RST,Writing a one activates the reset,0,w
RESET_CTRL1,21,1,SPIFI_RST,Writing a one activates the reset,0,w
RESET_CTRL1,22,1,CAN1_RST,Writing a one activates the reset,0,w
RESET_CTRL1,23,1,CAN0_RST,Writing a one activates the reset,0,w
RESET_CTRL1,24,1,M0APP_RST,Writing a one activates the reset,1,w
RESET_CTRL1,25,1,SGPIO_RST,Writing a one activates the reset,0,w
RESET_CTRL1,26,1,SPI_RST,Writing a one activates the reset,0,w
RESET_STATUS0,0,2,CORE_RST,Status of the CORE_RST reset generator output,0x0,rw
RESET_STATUS0,2,2,PERIPH_RST,Status of the PERIPH_RST reset generator output,0x0,rw
RESET_STATUS0,4,2,MASTER_RST,Status of the MASTER_RST reset generator output,0x1,rw
RESET_STATUS0,8,2,WWDT_RST,Status of the WWDT_RST reset generator output,0x0,rw
RESET_STATUS0,10,2,CREG_RST,Status of the CREG_RST reset generator output,0x0,rw
RESET_STATUS0,16,2,BUS_RST,Status of the BUS_RST reset generator output,0x1,rw
RESET_STATUS0,18,2,SCU_RST,Status of the SCU_RST reset generator output,0x1,rw
RESET_STATUS0,26,2,M4_RST,Status of the M4_RST reset generator output,0x1,rw
RESET_STATUS1,0,2,LCD_RST,Status of the LCD_RST reset generator output,0x1,rw
RESET_STATUS1,2,2,USB0_RST,Status of the USB0_RST reset generator output,0x1,rw
RESET_STATUS1,4,2,USB1_RST,Status of the USB1_RST reset generator output,0x1,rw
RESET_STATUS1,6,2,DMA_RST,Status of the DMA_RST reset generator output,0x1,rw
RESET_STATUS1,8,2,SDIO_RST,Status of the SDIO_RST reset generator output,0x1,rw
RESET_STATUS1,10,2,EMC_RST,Status of the EMC_RST reset generator output,0x1,rw
RESET_STATUS1,12,2,ETHERNET_RST,Status of the ETHERNET_RST reset generator output,0x1,rw
RESET_STATUS1,18,2,FLASHA_RST,Status of the FLASHA_RST reset generator output,0x1,
RESET_STATUS1,22,2,EEPROM_RST,Status of the EEPROM_RST reset generator output,0x1,
RESET_STATUS1,24,2,GPIO_RST,Status of the GPIO_RST reset generator output,0x1,rw
RESET_STATUS1,26,2,FLASHB_RST,Status of the FLASHB_RST reset generator output,0x1,rw
RESET_STATUS2,0,2,TIMER0_RST,Status of the TIMER0_RST reset generator output,0x1,rw
RESET_STATUS2,2,2,TIMER1_RST,Status of the TIMER1_RST reset generator output,0x1,rw
RESET_STATUS2,4,2,TIMER2_RST,Status of the TIMER2_RST reset generator output,0x1,rw
RESET_STATUS2,6,2,TIMER3_RST,Status of the TIMER3_RST reset generator output,0x1,rw
RESET_STATUS2,8,2,RITIMER_RST,Status of the RITIMER_RST reset generator output,0x1,rw
RESET_STATUS2,10,2,SCT_RST,Status of the SCT_RST reset generator output,0x1,rw
RESET_STATUS2,12,2,MOTOCONPWM_RST,Status of the MOTOCONPWM_RST reset generator output,0x1,rw
RESET_STATUS2,14,2,QEI_RST,Status of the QEI_RST reset generator output,0x1,rw
RESET_STATUS2,16,2,ADC0_RST,Status of the ADC0_RST reset generator output,0x1,rw
RESET_STATUS2,18,2,ADC1_RST,Status of the ADC1_RST reset generator output,0x1,rw
RESET_STATUS2,20,2,DAC_RST,Status of the DAC_RST reset generator output,0x1,rw
RESET_STATUS2,24,2,UART0_RST,Status of the UART0_RST reset generator output,0x1,rw
RESET_STATUS2,26,2,UART1_RST,Status of the UART1_RST reset generator output,0x1,rw
RESET_STATUS2,28,2,UART2_RST,Status of the UART2_RST reset generator output,0x1,rw
RESET_STATUS2,30,2,UART3_RST,Status of the UART3_RST reset generator output,0x1,rw
RESET_STATUS3,0,2,I2C0_RST,Status of the I2C0_RST reset generator output,0x1,rw
RESET_STATUS3,2,2,I2C1_RST,Status of the I2C1_RST reset generator output,0x1,rw
RESET_STATUS3,4,2,SSP0_RST,Status of the SSP0_RST reset generator output,0x1,rw
RESET_STATUS3,6,2,SSP1_RST,Status of the SSP1_RST reset generator output,0x1,rw
RESET_STATUS3,8,2,I2S_RST,Status of the I2S_RST reset generator output,0x1,rw
RESET_STATUS3,10,2,SPIFI_RST,Status of the SPIFI_RST reset generator output,0x1,rw
RESET_STATUS3,12,2,CAN1_RST,Status of the CAN1_RST reset generator output,0x1,rw
RESET_STATUS3,14,2,CAN0_RST,Status of the CAN0_RST reset generator output,0x1,rw
RESET_STATUS3,16,2,M0APP_RST,Status of the M0APP_RST reset generator output,0x3,rw
RESET_STATUS3,18,2,SGPIO_RST,Status of the SGPIO_RST reset generator output,0x1,rw
RESET_STATUS3,20,2,SPI_RST,Status of the SPI_RST reset generator output,0x1,rw
RESET_ACTIVE_STATUS0,0,1,CORE_RST,Current status of the CORE_RST,0,r
RESET_ACTIVE_STATUS0,1,1,PERIPH_RST,Current status of the PERIPH_RST,0,r
RESET_ACTIVE_STATUS0,2,1,MASTER_RST,Current status of the MASTER_RST,0,r
RESET_ACTIVE_STATUS0,4,1,WWDT_RST,Current status of the WWDT_RST,0,r
RESET_ACTIVE_STATUS0,5,1,CREG_RST,Current status of the CREG_RST,0,r
RESET_ACTIVE_STATUS0,8,1,BUS_RST,Current status of the BUS_RST,0,r
RESET_ACTIVE_STATUS0,9,1,SCU_RST,Current status of the SCU_RST,0,r
RESET_ACTIVE_STATUS0,13,1,M4_RST,Current status of the M4_RST,0,r
RESET_ACTIVE_STATUS0,16,1,LCD_RST,Current status of the LCD_RST,0,r
RESET_ACTIVE_STATUS0,17,1,USB0_RST,Current status of the USB0_RST,0,r
RESET_ACTIVE_STATUS0,18,1,USB1_RST,Current status of the USB1_RST,0,r
RESET_ACTIVE_STATUS0,19,1,DMA_RST,Current status of the DMA_RST,0,r
RESET_ACTIVE_STATUS0,20,1,SDIO_RST,Current status of the SDIO_RST,0,r
RESET_ACTIVE_STATUS0,21,1,EMC_RST,Current status of the EMC_RST,0,r
RESET_ACTIVE_STATUS0,22,1,ETHERNET_RST,Current status of the ETHERNET_RST,0,r
RESET_ACTIVE_STATUS0,25,1,FLASHA_RST,Current status of the FLASHA_RST,0,r
RESET_ACTIVE_STATUS0,27,1,EEPROM_RST,Current status of the EEPROM_RST,0,r
RESET_ACTIVE_STATUS0,28,1,GPIO_RST,Current status of the GPIO_RST,0,r
RESET_ACTIVE_STATUS0,29,1,FLASHB_RST,Current status of the FLASHB_RST,0,r
RESET_ACTIVE_STATUS1,0,1,TIMER0_RST,Current status of the TIMER0_RST,0,r
RESET_ACTIVE_STATUS1,1,1,TIMER1_RST,Current status of the TIMER1_RST,0,r
RESET_ACTIVE_STATUS1,2,1,TIMER2_RST,Current status of the TIMER2_RST,0,r
RESET_ACTIVE_STATUS1,3,1,TIMER3_RST,Current status of the TIMER3_RST,0,r
RESET_ACTIVE_STATUS1,4,1,RITIMER_RST,Current status of the RITIMER_RST,0,r
RESET_ACTIVE_STATUS1,5,1,SCT_RST,Current status of the SCT_RST,0,r
RESET_ACTIVE_STATUS1,6,1,MOTOCONPWM_RST,Current status of the MOTOCONPWM_RST,0,r
RESET_ACTIVE_STATUS1,7,1,QEI_RST,Current status of the QEI_RST,0,r
RESET_ACTIVE_STATUS1,8,1,ADC0_RST,Current status of the ADC0_RST,0,r
RESET_ACTIVE_STATUS1,9,1,ADC1_RST,Current status of the ADC1_RST,0,r
RESET_ACTIVE_STATUS1,10,1,DAC_RST,Current status of the DAC_RST,0,r
RESET_ACTIVE_STATUS1,12,1,UART0_RST,Current status of the UART0_RST,0,r
RESET_ACTIVE_STATUS1,13,1,UART1_RST,Current status of the UART1_RST,0,r
RESET_ACTIVE_STATUS1,14,1,UART2_RST,Current status of the UART2_RST,0,r
RESET_ACTIVE_STATUS1,15,1,UART3_RST,Current status of the UART3_RST,0,r
RESET_ACTIVE_STATUS1,16,1,I2C0_RST,Current status of the I2C0_RST,0,r
RESET_ACTIVE_STATUS1,17,1,I2C1_RST,Current status of the I2C1_RST,0,r
RESET_ACTIVE_STATUS1,18,1,SSP0_RST,Current status of the SSP0_RST,0,r
RESET_ACTIVE_STATUS1,19,1,SSP1_RST,Current status of the SSP1_RST,0,r
RESET_ACTIVE_STATUS1,20,1,I2S_RST,Current status of the I2S_RST,0,r
RESET_ACTIVE_STATUS1,21,1,SPIFI_RST,Current status of the SPIFI_RST,0,r
RESET_ACTIVE_STATUS1,22,1,CAN1_RST,Current status of the CAN1_RST,0,r
RESET_ACTIVE_STATUS1,23,1,CAN0_RST,Current status of the CAN0_RST,0,r
RESET_ACTIVE_STATUS1,24,1,M0APP_RST,Current status of the M0APP_RST,0,r
RESET_ACTIVE_STATUS1,25,1,SGPIO_RST,Current status of the SGPIO_RST,0,r
RESET_ACTIVE_STATUS1,26,1,SPI_RST,Current status of the SPI_RST,0,r
RESET_EXT_STAT0,0,1,EXT_RESET,Reset activated by external reset from reset pin,0,rw
RESET_EXT_STAT0,4,1,BOD_RESET,Reset activated by BOD reset,0,rw
RESET_EXT_STAT0,5,1,WWDT_RESET,Reset activated by WWDT time-out,0,rw
RESET_EXT_STAT1,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
RESET_EXT_STAT2,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT4,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
RESET_EXT_STAT5,1,1,CORE_RESET,Reset activated by CORE_RST output,0,rw
RESET_EXT_STAT8,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT9,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT13,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT16,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT17,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT18,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT19,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT20,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT21,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT22,3,1,MASTER_RESET,Reset activated by MASTER_RST output,0,rw
RESET_EXT_STAT25,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT27,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT28,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT29,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT32,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT33,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT34,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT35,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT36,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT37,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT38,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT39,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT40,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT41,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT42,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT44,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT45,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT46,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT47,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT48,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT49,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT50,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT51,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT52,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT53,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT54,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT55,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT56,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,,rw
RESET_EXT_STAT57,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
RESET_EXT_STAT58,2,1,PERIPHERAL_RESET,Reset activated by PERIPHERAL_RST output,0,rw
