114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
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/*
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* Copyright (C) 2023 Daniele Lacamera <root@danielinux.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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*
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* Author: Daniele Lacamera <root@danielinux.net>
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*/
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#include <stdint.h>
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#define MPU_BASE (0xE000ED90)
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extern uint32_t _end_stack;
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/* FAULT enable register SHCSR */
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#define SHCSR (*(volatile uint32_t *)(0xE000ED24))
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/* Bit to enable memory fault handler */
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#define MEMFAULT_ENABLE (1 << 16)
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/* MPU Registers */
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#define MPU_TYPE (*(volatile uint32_t *)(MPU_BASE + 0x00))
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#define MPU_CTRL (*(volatile uint32_t *)(MPU_BASE + 0x04))
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#define MPU_RNR (*(volatile uint32_t *)(MPU_BASE + 0x08))
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#define MPU_RBAR (*(volatile uint32_t *)(MPU_BASE + 0x0c))
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#define MPU_RASR (*(volatile uint32_t *)(MPU_BASE + 0x10))
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/* Some use-case specific values for RASR */
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#define RASR_ENABLED (1)
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#define RASR_RW (1 << 24)
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#define RASR_RDONLY (5 << 24)
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#define RASR_NOACCESS (0 << 24)
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#define RASR_SCB (7 << 16)
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#define RASR_SB (5 << 16)
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#define RASR_NOEXEC (1 << 28)
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/* Size */
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#define MPUSIZE_1K (0x09 << 1)
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#define MPUSIZE_2K (0x0a << 1)
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#define MPUSIZE_4K (0x0b << 1)
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#define MPUSIZE_8K (0x0c << 1)
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#define MPUSIZE_16K (0x0d << 1)
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#define MPUSIZE_32K (0x0e << 1)
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#define MPUSIZE_64K (0x0f << 1)
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#define MPUSIZE_128K (0x10 << 1)
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#define MPUSIZE_256K (0x11 << 1)
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#define MPUSIZE_512K (0x12 << 1)
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#define MPUSIZE_1M (0x13 << 1)
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#define MPUSIZE_2M (0x14 << 1)
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#define MPUSIZE_4M (0x15 << 1)
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#define MPUSIZE_8M (0x16 << 1)
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#define MPUSIZE_16M (0x17 << 1)
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#define MPUSIZE_32M (0x18 << 1)
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#define MPUSIZE_64M (0x19 << 1)
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#define MPUSIZE_128M (0x1a << 1)
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#define MPUSIZE_256M (0x1b << 1)
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#define MPUSIZE_512M (0x1c << 1)
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#define MPUSIZE_1G (0x1d << 1)
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#define MPUSIZE_2G (0x1e << 1)
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#define MPUSIZE_4G (0x1f << 1)
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#define STACK_SIZE (4 * 1024)
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static void mpu_set_region(int region, uint32_t start, uint32_t attr)
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{
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MPU_RNR = region;
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MPU_RBAR = start;
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MPU_RNR = region;
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MPU_RASR = attr;
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}
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int f7_mpu_enable(void)
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{
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volatile uint32_t type;
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volatile uint32_t start;
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volatile uint32_t attr;
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type = MPU_TYPE;
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if (type == 0) {
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/* MPU not present! */
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return -1;
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}
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/* Disable MPU to reconfigure regions */
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MPU_CTRL = 0;
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/* Set flash area as read-only, executable */
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start = 0;
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attr = RASR_ENABLED | MPUSIZE_4G | RASR_SCB | RASR_RW;
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mpu_set_region(0, start, attr);
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/* Enable the MPU, no background region */
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MPU_CTRL = 1;
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return 0;
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}
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