219 lines
9.3 KiB
C
219 lines
9.3 KiB
C
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/*
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* Copyright (C) 2023 Daniele Lacamera <root@danielinux.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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extern unsigned int _stored_data;
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extern unsigned int _start_data;
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extern unsigned int _end_data;
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extern unsigned int _start_bss;
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extern unsigned int _end_bss;
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extern unsigned int _end_stack;
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extern unsigned int _start_heap;
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static int zeroed_variable_in_bss;
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static int initialized_variable_in_data = 42;
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//#define STACK_PAINTING
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static volatile unsigned int avail_mem = 0;
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static unsigned int sp;
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extern void main(void);
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extern void isr_tim2(void);
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extern void isr_usart1(void);
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extern void isr_exti15_10(void);
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extern void isr_exti9_5(void);
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extern void isr_systick(void);
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extern void isr_exti2(void);
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extern void isr_exti3(void);
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extern void isr_exti0(void);
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extern void isr_exti4(void);
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void isr_reset(void) {
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register unsigned int *src, *dst;
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src = (unsigned int *) &_stored_data;
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dst = (unsigned int *) &_start_data;
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while (dst < (unsigned int *)&_end_data) {
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*dst = *src;
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dst++;
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src++;
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}
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dst = &_start_bss;
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while (dst < (unsigned int *)&_end_bss) {
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*dst = 0U;
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dst++;
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}
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avail_mem = &_end_stack - &_start_heap;
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main();
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}
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void isr_nmi(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_hardfault(void)
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{
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while(1);
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}
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void isr_memfault(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_busfault(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_usagefault(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_empty(void)
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{
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}
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__attribute__ ((section(".isr_vector")))
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void (* const IV[])(void) =
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{
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(void (*)(void))(&_end_stack),
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isr_reset, // Reset
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isr_nmi, // NMI
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isr_hardfault, // HardFault
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isr_memfault, // MemFault
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isr_busfault, // BusFault
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isr_usagefault, // UsageFault
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0, 0, 0, 0, // 4x reserved
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isr_empty, // SVC
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isr_empty, // DebugMonitor
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0, // reserved
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isr_empty, // PendSV
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isr_systick, // SysTick
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/* F7 Specific */
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isr_empty, // nvic_wwdg_isr(void);
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isr_empty, // pvd_isr(void);
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isr_empty, // tamp_stamp_isr(void);
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isr_empty, // rtc_wkup_isr(void);
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isr_empty, // flash_isr(void);
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isr_empty, // rcc_isr(void);
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isr_empty, // exti0_isr(void);
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isr_empty, // exti1_isr(void);
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isr_empty, // exti2_isr(void);
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isr_empty, // exti3_isr(void);
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isr_empty, // exti4_isr(void);
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isr_empty, // dma1_stream0_isr(void);
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isr_empty, // dma1_stream1_isr(void);
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isr_empty, // dma1_stream2_isr(void);
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isr_empty, // dma1_stream3_isr(void);
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isr_empty, // dma1_stream4_isr(void);
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isr_empty, // dma1_stream5_isr(void);
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isr_empty, // dma1_stream6_isr(void);
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isr_empty, // adc_isr(void);
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isr_empty, // can1_tx_isr(void);
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isr_empty, // can1_rx0_isr(void);
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isr_empty, // can1_rx1_isr(void);
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isr_empty, // can1_sce_isr(void);
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isr_exti9_5, // exti9_5_isr(void);
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isr_empty, // tim1_brk_tim9_isr(void);
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isr_empty, // tim1_up_tim10_isr(void);
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isr_empty, // tim1_trg_com_tim11_isr(void);
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isr_empty, // tim1_cc_isr(void);
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isr_tim2 , // tim2_isr(void);
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isr_empty, // tim3_isr(void);
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isr_empty, // tim4_isr(void);
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isr_empty, // i2c1_ev_isr(void);
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isr_empty, // i2c1_er_isr(void);
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isr_empty, // i2c2_ev_isr(void);
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isr_empty, // i2c2_er_isr(void);
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isr_empty, // spi1_isr(void);
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isr_empty, // spi2_isr(void);
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isr_usart1, // usart1_isr(void);
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isr_empty, // usart2_isr(void);
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isr_empty, // usart3_isr(void);
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isr_exti15_10, // exti15_10_isr(void);
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isr_empty, // rtc_alarm_isr(void);
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isr_empty, // usb_fs_wkup_isr(void);
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isr_empty, // tim8_brk_tim12_isr(void);
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isr_empty, // tim8_up_tim13_isr(void);
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isr_empty, // tim8_trg_com_tim14_isr(void);
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isr_empty, // tim8_cc_isr(void);
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isr_empty, // dma1_stream7_isr(void);
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isr_empty, // fsmc_isr(void);
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isr_empty, // sdmmc1_isr(void);
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isr_empty, // tim5_isr(void);
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isr_empty, // spi3_isr(void);
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isr_empty, // uart4_isr(void);
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isr_empty, // uart5_isr(void);
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isr_empty, // tim6_dac_isr(void);
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isr_empty, // tim7_isr(void);
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isr_empty, // dma2_stream0_isr(void);
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isr_empty, // dma2_stream1_isr(void);
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isr_empty, // dma2_stream2_isr(void);
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isr_empty, // dma2_stream3_isr(void);
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isr_empty, // dma2_stream4_isr(void);
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isr_empty, // eth_isr(void);
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isr_empty, // eth_wkup_isr(void);
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isr_empty, // can2_tx_isr(void);
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isr_empty, // can2_rx0_isr(void);
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isr_empty, // can2_rx1_isr(void);
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isr_empty, // can2_sce_isr(void);
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isr_empty, // otg_fs_isr(void);
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isr_empty, // dma2_stream5_isr(void);
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isr_empty, // dma2_stream6_isr(void);
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isr_empty, // dma2_stream7_isr(void);
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isr_empty, // usart6_isr(void);
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isr_empty, // i2c3_ev_isr(void);
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isr_empty, // i2c3_er_isr(void);
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isr_empty, // otg_hs_ep1_out_isr(void);
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isr_empty, // otg_hs_ep1_in_isr(void);
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isr_empty, // otg_hs_wkup_isr(void);
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isr_empty, // otg_hs_isr(void);
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isr_empty, // dcmi_isr(void);
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isr_empty, // cryp_isr(void);
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isr_empty, // hash_rng_isr(void);
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isr_empty, // fpu_isr(void);
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isr_empty, // uart7_isr(void);
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isr_empty, // uart8_isr(void);
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isr_empty, // spi4_isr(void);
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isr_empty, // spi5_isr(void);
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isr_empty, // spi6_isr(void);
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isr_empty, // sai1_isr(void);
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isr_empty, // lcd_tft_isr(void);
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isr_empty, // lcd_tft_err_isr(void);
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isr_empty, // dma2d_isr(void);
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isr_empty, // sai2_isr(void);
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isr_empty, // quadspi_isr(void);
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isr_empty, // i2c4_ev_isr(void);
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isr_empty, // i2c4_er_isr(void);
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isr_empty, // spdifrx_isr(void);
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};
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