424 lines
18 KiB
C
424 lines
18 KiB
C
/**
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******************************************************************************
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* @file stm32f7xx_hal_cortex.h
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* @author MCD Application Team
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* @version V1.2.0
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* @date 30-December-2016
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* @brief Header file of CORTEX HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F7xx_HAL_CORTEX_H
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#define __STM32F7xx_HAL_CORTEX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal_def.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup CORTEX
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup CORTEX_Exported_Types Cortex Exported Types
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* @{
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*/
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#if (__MPU_PRESENT == 1)
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/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
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* @brief MPU Region initialization structure
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* @{
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*/
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typedef struct
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{
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uint8_t Enable; /*!< Specifies the status of the region.
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This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
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uint8_t Number; /*!< Specifies the number of the region to protect.
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This parameter can be a value of @ref CORTEX_MPU_Region_Number */
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uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
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uint8_t Size; /*!< Specifies the size of the region to protect.
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This parameter can be a value of @ref CORTEX_MPU_Region_Size */
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uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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uint8_t TypeExtField; /*!< Specifies the TEX field level.
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This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
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uint8_t AccessPermission; /*!< Specifies the region access permission type.
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This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
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uint8_t DisableExec; /*!< Specifies the instruction access status.
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This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
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uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
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This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
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uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
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This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
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uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
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This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
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}MPU_Region_InitTypeDef;
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/**
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* @}
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*/
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#endif /* __MPU_PRESENT */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
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* @{
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*/
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/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
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* @{
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*/
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#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
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0 bits for subpriority */
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/**
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* @}
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*/
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/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
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* @{
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*/
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#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
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#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
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/**
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* @}
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*/
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#if (__MPU_PRESENT == 1)
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/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
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* @{
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*/
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#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
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#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
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#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
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#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
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* @{
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*/
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#define MPU_REGION_ENABLE ((uint8_t)0x01U)
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#define MPU_REGION_DISABLE ((uint8_t)0x00U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
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* @{
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*/
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#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
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#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
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* @{
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*/
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#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
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#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
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* @{
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*/
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#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
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#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
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* @{
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*/
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#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
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#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
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* @{
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*/
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#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
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#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
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#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
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* @{
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*/
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#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
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#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
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#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
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#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
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#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
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#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
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#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
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#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
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#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
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#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
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#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
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#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
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#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
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#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
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#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
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#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
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#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
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#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
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#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
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#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
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#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
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#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
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#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
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#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
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#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
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#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
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#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
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#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
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* @{
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*/
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#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
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#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
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#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
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#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
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#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
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#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
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/**
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* @}
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*/
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/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
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* @{
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*/
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#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
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#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
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#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
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#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
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#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
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#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
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#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
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#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
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/**
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* @}
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*/
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#endif /* __MPU_PRESENT */
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/**
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* @}
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*/
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/* Exported Macros -----------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup CORTEX_Exported_Functions
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* @{
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*/
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/** @addtogroup CORTEX_Exported_Functions_Group1
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* @{
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*/
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/* Initialization and de-initialization functions *****************************/
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void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
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void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
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void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
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void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
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void HAL_NVIC_SystemReset(void);
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uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
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/**
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* @}
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*/
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/** @addtogroup CORTEX_Exported_Functions_Group2
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* @{
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*/
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/* Peripheral Control functions ***********************************************/
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#if (__MPU_PRESENT == 1)
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void HAL_MPU_Enable(uint32_t MPU_Control);
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void HAL_MPU_Disable(void);
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void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
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#endif /* __MPU_PRESENT */
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uint32_t HAL_NVIC_GetPriorityGrouping(void);
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void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
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uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
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void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
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void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
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uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
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void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
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void HAL_SYSTICK_IRQHandler(void);
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void HAL_SYSTICK_Callback(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
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* @{
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*/
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#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
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((GROUP) == NVIC_PRIORITYGROUP_1) || \
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((GROUP) == NVIC_PRIORITYGROUP_2) || \
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((GROUP) == NVIC_PRIORITYGROUP_3) || \
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((GROUP) == NVIC_PRIORITYGROUP_4))
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#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
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#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
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#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
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#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
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((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
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#if (__MPU_PRESENT == 1)
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#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
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((STATE) == MPU_REGION_DISABLE))
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#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
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((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
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#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
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((STATE) == MPU_ACCESS_NOT_SHAREABLE))
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#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
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((STATE) == MPU_ACCESS_NOT_CACHEABLE))
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#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
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((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
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#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
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((TYPE) == MPU_TEX_LEVEL1) || \
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((TYPE) == MPU_TEX_LEVEL2))
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#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
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((TYPE) == MPU_REGION_PRIV_RW) || \
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((TYPE) == MPU_REGION_PRIV_RW_URO) || \
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((TYPE) == MPU_REGION_FULL_ACCESS) || \
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((TYPE) == MPU_REGION_PRIV_RO) || \
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((TYPE) == MPU_REGION_PRIV_RO_URO))
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#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
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((NUMBER) == MPU_REGION_NUMBER1) || \
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((NUMBER) == MPU_REGION_NUMBER2) || \
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((NUMBER) == MPU_REGION_NUMBER3) || \
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((NUMBER) == MPU_REGION_NUMBER4) || \
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((NUMBER) == MPU_REGION_NUMBER5) || \
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((NUMBER) == MPU_REGION_NUMBER6) || \
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((NUMBER) == MPU_REGION_NUMBER7))
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#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
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((SIZE) == MPU_REGION_SIZE_64B) || \
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((SIZE) == MPU_REGION_SIZE_128B) || \
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((SIZE) == MPU_REGION_SIZE_256B) || \
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((SIZE) == MPU_REGION_SIZE_512B) || \
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((SIZE) == MPU_REGION_SIZE_1KB) || \
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((SIZE) == MPU_REGION_SIZE_2KB) || \
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((SIZE) == MPU_REGION_SIZE_4KB) || \
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((SIZE) == MPU_REGION_SIZE_8KB) || \
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((SIZE) == MPU_REGION_SIZE_16KB) || \
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((SIZE) == MPU_REGION_SIZE_32KB) || \
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((SIZE) == MPU_REGION_SIZE_64KB) || \
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((SIZE) == MPU_REGION_SIZE_128KB) || \
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((SIZE) == MPU_REGION_SIZE_256KB) || \
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((SIZE) == MPU_REGION_SIZE_512KB) || \
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((SIZE) == MPU_REGION_SIZE_1MB) || \
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((SIZE) == MPU_REGION_SIZE_2MB) || \
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((SIZE) == MPU_REGION_SIZE_4MB) || \
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((SIZE) == MPU_REGION_SIZE_8MB) || \
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((SIZE) == MPU_REGION_SIZE_16MB) || \
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((SIZE) == MPU_REGION_SIZE_32MB) || \
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((SIZE) == MPU_REGION_SIZE_64MB) || \
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((SIZE) == MPU_REGION_SIZE_128MB) || \
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((SIZE) == MPU_REGION_SIZE_256MB) || \
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((SIZE) == MPU_REGION_SIZE_512MB) || \
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((SIZE) == MPU_REGION_SIZE_1GB) || \
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((SIZE) == MPU_REGION_SIZE_2GB) || \
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((SIZE) == MPU_REGION_SIZE_4GB))
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#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
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#endif /* __MPU_PRESENT */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F7xx_HAL_CORTEX_H */
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