139 lines
2.8 KiB
YAML
139 lines
2.8 KiB
YAML
!!omap
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- SPI_CR:
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fields: !!omap
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- BITENABLE:
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access: rw
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description: Bit length enable
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lsb: 2
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reset_value: '0'
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width: 1
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- CPHA:
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access: rw
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description: Clock phase control
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lsb: 3
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reset_value: '0'
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width: 1
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- CPOL:
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access: rw
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description: Clock polarity control
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lsb: 4
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reset_value: '0'
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width: 1
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- MSTR:
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access: rw
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description: Master mode select
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lsb: 5
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reset_value: '0'
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width: 1
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- LSBF:
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access: rw
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description: LSB first
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lsb: 6
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reset_value: '0'
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width: 1
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- SPIE:
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access: rw
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description: Serial peripheral interrupt enable
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lsb: 7
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reset_value: '0'
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width: 1
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- BITS:
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access: rw
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description: Bits per transfer
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lsb: 8
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reset_value: '0'
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width: 4
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- SPIF:
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access: rw
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description: Interrupt
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lsb: 0
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reset_value: '0'
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width: 1
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- SPI_SR:
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fields: !!omap
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- ABRT:
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access: ro
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description: Slave abort
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lsb: 3
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reset_value: '0'
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width: 1
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- MODF:
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access: ro
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description: Mode fault
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lsb: 4
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reset_value: '0'
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width: 1
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- ROVR:
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access: ro
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description: Read overrun
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lsb: 5
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reset_value: '0'
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width: 1
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- WCOL:
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access: ro
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description: Write collision
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lsb: 6
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reset_value: '0'
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width: 1
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- SPIF:
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access: ro
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description: Transfer complete
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lsb: 7
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reset_value: '0'
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width: 1
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- SPI_DR:
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fields: !!omap
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- DATA:
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access: rw
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description: Bi-directional data port
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lsb: 0
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reset_value: '0'
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width: 16
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- SPI_CCR:
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fields: !!omap
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- COUNTER:
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access: rw
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description: Clock counter setting
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lsb: 0
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reset_value: '0'
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width: 8
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- SPI_TCR:
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fields: !!omap
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- TEST:
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access: rw
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description: Test mode
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lsb: 1
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reset_value: '0'
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width: 7
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- SPI_TSR:
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fields: !!omap
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- ABRT:
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access: rw
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description: Slave abort
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lsb: 3
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reset_value: '0'
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width: 1
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- MODF:
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access: rw
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description: Mode fault
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lsb: 4
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reset_value: '0'
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width: 1
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- ROVR:
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access: rw
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description: Read overrun
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lsb: 5
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reset_value: '0'
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width: 1
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- WCOL:
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access: rw
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description: Write collision
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lsb: 6
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reset_value: '0'
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width: 1
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- SPIF:
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access: rw
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description: Transfer complete
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lsb: 7
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reset_value: '0'
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width: 1
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