410 lines
9.3 KiB
C
410 lines
9.3 KiB
C
/** @defgroup STM32L0xx-rcc-file RCC
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*
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* @ingroup STM32L0xx
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*
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* @brief <b>unicore-mx STM32L0xx Reset and Clock Control</b>
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*
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* @version 1.0.0
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*
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* @date November 2014
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*
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* This library supports the Reset and Clock Control System in the STM32F0xx
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* series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <unicore-mx/cm3/assert.h>
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#include <unicore-mx/stm32/rcc.h>
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_MSI:
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RCC_CR |= RCC_CR_MSION;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI48:
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RCC_CRRCR |= RCC_CRRCR_HSI48ON;
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break;
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case RCC_HSI16:
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RCC_CR |= RCC_CR_HSI16ON;
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break;
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case RCC_LSE:
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RCC_CSR |= RCC_CSR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_MSI:
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RCC_CR &= ~RCC_CR_MSION;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI48:
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RCC_CRRCR &= ~RCC_CRRCR_HSI48ON;
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break;
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case RCC_HSI16:
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RCC_CR &= ~RCC_CR_HSI16ON;
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break;
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case RCC_LSE:
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RCC_CSR &= ~RCC_CSR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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/* TODO easy target for shared code */
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void rcc_osc_bypass_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_CSR |= RCC_CSR_LSEBYP;
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break;
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default:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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/* TODO easy target for shared code */
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void rcc_osc_bypass_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_CSR &= ~RCC_CSR_LSEBYP;
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break;
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default:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Clear the Oscillator Ready Interrupt Flag
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*
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* Clear the interrupt flag that was set when a clock oscillator became ready
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* to use.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CICR |= RCC_CICR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CICR |= RCC_CICR_HSERDYC;
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break;
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case RCC_HSI48:
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RCC_CICR |= RCC_CICR_HSI48RDYC;
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break;
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case RCC_HSI16:
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RCC_CICR |= RCC_CICR_HSI16RDYC;
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break;
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case RCC_MSI:
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RCC_CICR |= RCC_CICR_MSIRDYC;
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break;
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case RCC_LSE:
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RCC_CICR |= RCC_CICR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CICR |= RCC_CICR_LSIRDYC;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable the Oscillator Ready Interrupt
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER |= RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER |= RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI48:
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RCC_CIER |= RCC_CIER_HSI48RDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER |= RCC_CIER_HSI16RDYIE;
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break;
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case RCC_MSI:
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RCC_CIER |= RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER |= RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER |= RCC_CIER_LSIRDYIE;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable the Oscillator Ready Interrupt
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER &= ~RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER &= ~RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI48:
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RCC_CIER &= ~RCC_CIER_HSI48RDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER &= ~RCC_CIER_HSI16RDYIE;
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break;
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case RCC_MSI:
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RCC_CIER &= ~RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER &= ~RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER &= ~RCC_CIER_LSIRDYIE;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Read the Oscillator Ready Interrupt Flag
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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* @returns int. Boolean value for flag set.
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*/
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
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break;
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case RCC_HSI48:
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return ((RCC_CIFR & RCC_CIFR_HSI48RDYF) != 0);
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break;
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case RCC_HSI16:
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return ((RCC_CIFR & RCC_CIFR_HSI16RDYF) != 0);
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break;
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case RCC_MSI:
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return ((RCC_CIFR & RCC_CIFR_MSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
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break;
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}
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cm3_assert_not_reached();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Wait for Oscillator Ready.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case RCC_HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case RCC_HSI16:
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while ((RCC_CR & RCC_CR_HSI16RDY) == 0);
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break;
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case RCC_HSI48:
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while ((RCC_CRRCR & RCC_CRRCR_HSI48RDY) == 0);
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break;
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case RCC_MSI:
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while ((RCC_CR & RCC_CR_MSIRDY) == 0);
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break;
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case RCC_LSE:
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while ((RCC_CSR & RCC_CSR_LSERDY) == 0);
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break;
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case RCC_LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set HSI48 clock source to the RC48 (CRS)
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*/
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void rcc_set_hsi48_source_rc48(void)
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{
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RCC_CCIPR |= RCC_CCIPR_HSI48SEL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set HSI48 clock source to the PLL
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*/
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void rcc_set_hsi48_source_pll(void)
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{
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RCC_CCIPR &= ~RCC_CCIPR_HSI48SEL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the Source for the System Clock.
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*
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* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, HSI16, MSI and PLL have
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* effect.
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*/
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void rcc_set_sysclk_source(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CFGR |= RCC_CFGR_SW_PLL;
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break;
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case RCC_HSE:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSE;
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break;
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case RCC_HSI16:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSI16;
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break;
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case RCC_MSI:
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RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_MSI;
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break;
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case RCC_HSI48:
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case RCC_LSE:
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case RCC_LSI:
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Multiplication Factor.
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*
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* @note This only has effect when the PLL is disabled.
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*
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* @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll_multiplier(uint32_t factor)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
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RCC_CFGR = reg | (factor << RCC_CFGR_PLLMUL_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Division Factor.
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*
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* @note This only has effect when the PLL is disabled.
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*
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* @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pdf
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*/
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void rcc_set_pll_divider(uint32_t factor)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
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RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB1 Prescale Factor.
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*
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* @note The APB1 clock frequency must not exceed 32MHz.
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*
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* @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre
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*/
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void rcc_set_ppre1(uint32_t ppre)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE1_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB2 Prescale Factor.
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*
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* @note The APB2 clock frequency must not exceed 32MHz.
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*
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* @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb2pre
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*/
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void rcc_set_ppre2(uint32_t ppre)
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{
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uint32_t reg = RCC_CFGR
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& ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE2_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the AHB Prescale Factor.
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*
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* @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
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*/
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg = RCC_CFGR & ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT);
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}
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/**@}*/
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