567 lines
13 KiB
C
567 lines
13 KiB
C
/** @defgroup STM32L1xx-rcc-file RCC
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@ingroup STM32L1xx
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@brief <b>unicore-mx STM32F1xx Reset and Clock Control</b>
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@version 1.0.0
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This library supports the Reset and Clock Control System in the STM32L1xx
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series of ARM Cortex Microcontrollers by ST Microelectronics.
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Clock settings and resets for many peripherals are given here rather than in
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the corresponding peripheral library.
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The library also provides a number of common configurations for the processor
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system clock. Not all possible configurations are included.
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*/
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/*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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* Based on the F4 code...
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*/
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/**@{*/
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#include <unicore-mx/stm32/rcc.h>
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#include <unicore-mx/stm32/flash.h>
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#include <unicore-mx/stm32/pwr.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 2097000;
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uint32_t rcc_apb1_frequency = 2097000;
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uint32_t rcc_apb2_frequency = 2097000;
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const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
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{ /* 24MHz PLL from HSI */
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.pll_mul = RCC_CFGR_PLLMUL_MUL3,
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.pll_div = RCC_CFGR_PLLDIV_DIV2,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_LATENCY_1WS,
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.ahb_frequency = 24000000,
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.apb1_frequency = 24000000,
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.apb2_frequency = 24000000,
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},
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{ /* 32MHz PLL from HSI */
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.pll_mul = RCC_CFGR_PLLMUL_MUL6,
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.pll_div = RCC_CFGR_PLLDIV_DIV3,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_LATENCY_1WS,
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.ahb_frequency = 32000000,
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.apb1_frequency = 32000000,
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.apb2_frequency = 32000000,
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},
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{ /* 16MHz HSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.ahb_frequency = 16000000,
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.apb1_frequency = 16000000,
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.apb2_frequency = 16000000,
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},
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{ /* 4MHz HSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_DIV4,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.ahb_frequency = 4000000,
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.apb1_frequency = 4000000,
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.apb2_frequency = 4000000,
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},
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{ /* 4MHz MSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.ahb_frequency = 4194000,
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.apb1_frequency = 4194000,
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.apb2_frequency = 4194000,
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.msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
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},
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{ /* 2MHz MSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.ahb_frequency = 2097000,
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.apb1_frequency = 2097000,
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.apb2_frequency = 2097000,
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.msi_range = RCC_ICSCR_MSIRANGE_2MHZ,
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},
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};
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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case RCC_MSI:
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RCC_CIR |= RCC_CIR_MSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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case RCC_MSI:
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RCC_CIR |= RCC_CIR_MSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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case RCC_MSI:
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RCC_CIR &= ~RCC_CIR_MSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case RCC_HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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case RCC_MSI:
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return ((RCC_CIR & RCC_CIR_MSIRDYF) != 0);
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break;
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}
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/* Shouldn't be reached. */
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return -1;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case RCC_HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case RCC_HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case RCC_MSI:
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while ((RCC_CR & RCC_CR_MSIRDY) == 0);
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break;
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case RCC_LSE:
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while ((RCC_CSR & RCC_CSR_LSERDY) == 0);
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break;
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case RCC_LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
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RCC_CFGR_SWS_SYSCLKSEL_PLLCLK);
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break;
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case RCC_HSE:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
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RCC_CFGR_SWS_SYSCLKSEL_HSECLK);
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break;
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case RCC_HSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
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RCC_CFGR_SWS_SYSCLKSEL_HSICLK);
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break;
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case RCC_MSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
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RCC_CFGR_SWS_SYSCLKSEL_MSICLK);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_MSI:
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RCC_CR |= RCC_CR_MSION;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_CSR |= RCC_CSR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_MSI:
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RCC_CR &= ~RCC_CR_MSION;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_CSR &= ~RCC_CSR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_CSR |= RCC_CSR_LSEBYP;
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break;
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case RCC_PLL:
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case RCC_HSI:
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case RCC_LSI:
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case RCC_MSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_osc_bypass_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_CSR &= ~RCC_CSR_LSEBYP;
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break;
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case RCC_PLL:
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case RCC_HSI:
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case RCC_LSI:
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case RCC_MSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_set_sysclk_source(uint32_t clk)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier,
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uint32_t divisor)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
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reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
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reg32 &= ~(1 << 16);
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reg32 |= (source << 16);
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reg32 |= (multiplier << RCC_CFGR_PLLMUL_SHIFT);
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reg32 |= (divisor << RCC_CFGR_PLLDIV_SHIFT);
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RCC_CFGR = reg32;
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}
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 16);
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
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void rcc_set_ppre2(uint32_t ppre2)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11));
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RCC_CFGR = (reg32 | (ppre2 << 11));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8));
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RCC_CFGR = (reg32 | (ppre1 << 8));
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}
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
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RCC_CFGR = (reg32 | (hpre << 4));
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}
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void rcc_set_rtcpre(uint32_t rtcpre)
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{
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uint32_t reg32;
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reg32 = RCC_CR;
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reg32 &= ~((1 << 30) | (1 << 29));
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RCC_CR = (reg32 | (rtcpre << 29));
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}
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uint32_t rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return (RCC_CFGR & 0x000c) >> 2;
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}
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void rcc_rtc_select_clock(uint32_t clock)
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{
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RCC_CSR &= ~(RCC_CSR_RTCSEL_MASK << RCC_CSR_RTCSEL_SHIFT);
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RCC_CSR |= (clock << RCC_CSR_RTCSEL_SHIFT);
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}
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void rcc_clock_setup_msi(const struct rcc_clock_scale *clock)
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{
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/* Enable internal multi-speed oscillator. */
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uint32_t reg = RCC_ICSCR;
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reg &= ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
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reg |= (clock->msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
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RCC_ICSCR = reg;
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rcc_osc_on(RCC_MSI);
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rcc_wait_for_osc_ready(RCC_MSI);
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/* Select MSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_MSICLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
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pwr_set_vos_scale(clock->voltage_scale);
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/* I guess this should be in the settings? */
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flash_64bit_enable();
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flash_prefetch_enable();
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/* Configure flash settings. */
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flash_set_ws(clock->flash_config);
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/* Set the peripheral clock frequencies used. */
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rcc_ahb_frequency = clock->ahb_frequency;
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rcc_apb1_frequency = clock->apb1_frequency;
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rcc_apb2_frequency = clock->apb2_frequency;
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}
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void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(RCC_HSI);
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rcc_wait_for_osc_ready(RCC_HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
|
|
|
|
/*
|
|
* Set prescalers for AHB, ADC, ABP1, ABP2.
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|
* Do this before touching the PLL (TODO: why?).
|
|
*/
|
|
rcc_set_hpre(clock->hpre);
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|
rcc_set_ppre1(clock->ppre1);
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|
rcc_set_ppre2(clock->ppre2);
|
|
|
|
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
|
|
pwr_set_vos_scale(clock->voltage_scale);
|
|
|
|
/* I guess this should be in the settings? */
|
|
flash_64bit_enable();
|
|
flash_prefetch_enable();
|
|
/* Configure flash settings. */
|
|
flash_set_ws(clock->flash_config);
|
|
|
|
/* Set the peripheral clock frequencies used. */
|
|
rcc_ahb_frequency = clock->ahb_frequency;
|
|
rcc_apb1_frequency = clock->apb1_frequency;
|
|
rcc_apb2_frequency = clock->apb2_frequency;
|
|
}
|
|
|
|
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
|
|
{
|
|
/* Turn on the appropriate source for the PLL */
|
|
if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
|
|
rcc_osc_on(RCC_HSE);
|
|
rcc_wait_for_osc_ready(RCC_HSE);
|
|
} else {
|
|
rcc_osc_on(RCC_HSI);
|
|
rcc_wait_for_osc_ready(RCC_HSI);
|
|
}
|
|
|
|
/*
|
|
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
|
* Do this before touching the PLL (TODO: why?).
|
|
*/
|
|
rcc_set_hpre(clock->hpre);
|
|
rcc_set_ppre1(clock->ppre1);
|
|
rcc_set_ppre2(clock->ppre2);
|
|
|
|
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
|
|
pwr_set_vos_scale(clock->voltage_scale);
|
|
|
|
/* I guess this should be in the settings? */
|
|
flash_64bit_enable();
|
|
flash_prefetch_enable();
|
|
/* Configure flash settings. */
|
|
flash_set_ws(clock->flash_config);
|
|
|
|
rcc_set_pll_configuration(clock->pll_source, clock->pll_mul,
|
|
clock->pll_div);
|
|
|
|
/* Enable PLL oscillator and wait for it to stabilize. */
|
|
rcc_osc_on(RCC_PLL);
|
|
rcc_wait_for_osc_ready(RCC_PLL);
|
|
|
|
/* Select PLL as SYSCLK source. */
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
|
|
|
|
/* Set the peripheral clock frequencies used. */
|
|
rcc_ahb_frequency = clock->ahb_frequency;
|
|
rcc_apb1_frequency = clock->apb1_frequency;
|
|
rcc_apb2_frequency = clock->apb2_frequency;
|
|
}
|
|
|
|
/**@}*/
|