target-f746.ld 1.0 KB

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  1. MEMORY
  2. {
  3. FLASH(rx) : ORIGIN = 0x08000000, LENGTH = 0xC0000
  4. DFLASH(RX) : ORIGIN = 0x080C0000, LENGTH = 0x40000
  5. SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x50000
  6. SDRAM(rwx) : ORIGIN = 0xC0000000, LENGTH = 0x800000
  7. }
  8. GROUP(libgcc.a libc.a libm.a)
  9. SECTIONS
  10. {
  11. .text :
  12. {
  13. _start_text = .;
  14. KEEP(*(.isr_vector))
  15. *(.init)
  16. *(.fini)
  17. *(.text*)
  18. *(.rodata*)
  19. . = ALIGN(4);
  20. _end_text = .;
  21. } > FLASH
  22. .edidx :
  23. {
  24. . = ALIGN(4);
  25. *(.ARM.exidx*)
  26. } > FLASH
  27. _stored_data = .;
  28. .data : AT (_stored_data)
  29. {
  30. _start_data = .;
  31. *(.data*)
  32. . = ALIGN(4);
  33. _end_data = .;
  34. } > SRAM
  35. .bss :
  36. {
  37. _start_bss = .;
  38. *(.bss*)
  39. *(COMMON)
  40. . = ALIGN(4);
  41. _end_bss = .;
  42. _end = .;
  43. end = .;
  44. } > SRAM
  45. }
  46. PROVIDE(_end_stack = ORIGIN(SRAM) + LENGTH(SRAM));
  47. PROVIDE(_start_heap = ORIGIN(SDRAM) + 7M);