#ifndef SYSTEM_H_INCLUDED #define SYSTEM_H_INCLUDED #include /* System specific: PLL with 8 MHz external oscillator, CPU at 168MHz */ #define PLL_FULL_MASK (0x7F037FFF) extern uint32_t cpu_freq; void panic(void); void printbin(const uint8_t *buf, int len); /* Defined in uart.c */ extern int _mutex_lock(void *); /* defined in mutex.S */ extern int _mutex_unlock(void *); /* PIN CONFIG TARGET */ #define LED 5 // PA5 #define SPI_FLASH_PIN 4 /* Flash CS connected to GPIOA4 */ #define SPI1_PIN_AF 5 #define SPI1_CLOCK_PIN 5 #define SPI1_MISO_PIN 6 #define SPI1_MOSI_PIN 7 #define SPI2_PIN_AF 5 #define SPI2_CLOCK_PIN 13 #define SPI2_MISO_PIN 14 #define SPI2_MOSI_PIN 15 #define I2C1_PIN_AF 4 #define I2C1_SDA 9 /* GPIOB P9 */ #define I2C1_SCL 8 /* GPIOB P8 */ #define GPIO_MODE_AF (2) /* STM32 specific defines */ #define APB1_CLOCK_ER (*(volatile uint32_t *)(0x40023840)) #define APB1_CLOCK_RST (*(volatile uint32_t *)(0x40023820)) #define TIM2_APB1_CLOCK_ER_VAL (1 << 0) #define TIM4_APB1_CLOCK_ER_VAL (1 << 2) #define PWR_APB1_CLOCK_ER_VAL (1 << 28) #define SPI2_APB1_CLOCK_ER_VAL (1 << 14) #define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844)) #define APB2_CLOCK_RST (*(volatile uint32_t *)(0x40023824)) #define SYSCFG_APB2_CLOCK_ER (1 << 14) #define SPI1_APB2_CLOCK_ER_VAL (1 << 12) #define SDIO_APB2_CLOCK_ER_VAL (1 << 11) #define ADC1_APB2_CLOCK_ER_VAL (1 << 8) #define RCC_BACKUP (*(volatile uint32_t *)(0x40023870)) #define RCC_BACKUP_RESET (1 << 16) #define RCC_BACKUP_RTCEN (1 << 15) #define RCC_BACKUP_RTCSEL_SHIFT 8 #define RCC_BACKUP_RTCSEL_MASK 0x3 #define RCC_BACKUP_RTCSEL_NONE 0 #define RCC_BACKUP_RTCSEL_LSE 1 #define RCC_BACKUP_RTCSEL_LSI 2 #define RCC_BACKUP_RTCSEL_HSE 3 #define RCC_BACKUP_LSEMOD (1 << 3) #define RCC_BACKUP_LSEBYP (1 << 2) #define RCC_BACKUP_LSERDY (1 << 1) #define RCC_BACKUP_LSEON (1 << 0) #define RCC_CSR_LSION (1 << 0) #define RCC_CSR_LSIRDY (1 << 1) /* EXTI */ #define EXTI_CR_BASE (0x40013808) #define EXTI_CR0 (*(volatile uint32_t *)(EXTI_CR_BASE + 0x00)) #define EXTI_CR_EXTI0_MASK (0xFFFF) #define EXTI_IMR (*(volatile uint32_t *)(EXTI_BASE + 0x00)) #define EXTI_EMR (*(volatile uint32_t *)(EXTI_BASE + 0x04)) #define EXTI_RTSR (*(volatile uint32_t *)(EXTI_BASE + 0x08)) #define EXTI_FTSR (*(volatile uint32_t *)(EXTI_BASE + 0x0c)) #define EXTI_SWIER (*(volatile uint32_t *)(EXTI_BASE + 0x10)) #define EXTI_PR (*(volatile uint32_t *)(EXTI_BASE + 0x14)) /* HW RNG */ #define RNG_BASE (0x50060800) #define RNG_CR (*(volatile uint32_t *)(RNG_BASE + 0x00)) #define RNG_SR (*(volatile uint32_t *)(RNG_BASE + 0x04)) #define RNG_DR (*(volatile uint32_t *)(RNG_BASE + 0x08)) #define RNG_CR_IE (1 << 3) #define RNG_CR_RNGEN (1 << 2) #define RNG_SR_DRDY (1 << 0) #define RNG_SR_CECS (1 << 1) #define RNG_SR_SECS (1 << 2) /* SCB for sleep configuration */ #define SCB_SCR (*(volatile uint32_t *)(0xE000ED10)) #define SCB_SCR_SEVONPEND (1 << 4) #define SCB_SCR_SLEEPDEEP (1 << 2) #define SCB_SCR_SLEEPONEXIT (1 << 1) /* Assembly helpers */ #define DMB() __asm__ volatile ("dmb") #define WFI() __asm__ volatile ("wfi") #define WFE() __asm__ volatile ("wfe") #define SEV() __asm__ volatile ("sev") /* Master clock setting */ void clock_pll_on(void); void clock_pll_off(void); /* NVIC */ /* NVIC ISER Base register (Cortex-M) */ #define NVIC_RTC_IRQ (3) #define NVIC_TIM2_IRQN (28) #define NVIC_ISER_BASE (0xE000E100) #define NVIC_ICER_BASE (0xE000E180) #define NVIC_ICPR_BASE (0xE000E280) #define NVIC_IPRI_BASE (0xE000E400) #define NVIC_EXTI0_IRQ (6) #define NVIC_EXTI9_5_IRQ (23) #define NVIC_EXTI15_10_IRQ (40) static inline void nvic_irq_enable(uint8_t n) { int i = n / 32; volatile uint32_t *nvic_iser = ((volatile uint32_t *)(NVIC_ISER_BASE + 4 * i)); *nvic_iser |= (1 << (n % 32)); } static inline void nvic_irq_disable(uint8_t n) { int i = n / 32; volatile uint32_t *nvic_icer = ((volatile uint32_t *)(NVIC_ICER_BASE + 4 * i)); *nvic_icer |= (1 << (n % 32)); } static inline void nvic_irq_setprio(uint8_t n, uint8_t prio) { volatile uint8_t *nvic_ipri = ((volatile uint8_t *)(NVIC_IPRI_BASE + n)); *nvic_ipri = prio; } static inline void nvic_irq_clear(uint8_t n) { int i = n / 32; volatile uint8_t *nvic_icpr = ((volatile uint8_t *)(NVIC_ICPR_BASE + 4 * i)); *nvic_icpr = (1 << (n % 32)); } /*** FLASH ***/ #define FLASH_BASE (0x40023C00) #define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) #define FLASH_ACR_ENABLE_DATA_CACHE (1 << 10) #define FLASH_ACR_ENABLE_INST_CACHE (1 << 9) /*** SPI ***/ #define SPI1 (0x40013000) #define SPI1_CR1 (*(volatile uint32_t *)(SPI1)) #define SPI1_CR2 (*(volatile uint32_t *)(SPI1 + 0x04)) #define SPI1_SR (*(volatile uint32_t *)(SPI1 + 0x08)) #define SPI1_DR (*(volatile uint32_t *)(SPI1 + 0x0c)) #define SPI2 (0x40003800) #define SPI2_CR1 (*(volatile uint32_t *)(SPI2)) #define SPI2_CR2 (*(volatile uint32_t *)(SPI2 + 0x04)) #define SPI2_SR (*(volatile uint32_t *)(SPI2 + 0x08)) #define SPI2_DR (*(volatile uint32_t *)(SPI2 + 0x0c)) #define SPI_CR1_CLOCK_PHASE (1 << 0) #define SPI_CR1_CLOCK_POLARITY (1 << 1) #define SPI_CR1_MASTER (1 << 2) #define SPI_CR1_BAUDRATE (0x07 << 3) #define SPI_CR1_SPI_EN (1 << 6) #define SPI_CR1_LSBFIRST (1 << 7) #define SPI_CR1_SSI (1 << 8) #define SPI_CR1_SSM (1 << 9) #define SPI_CR1_16BIT_FORMAT (1 << 11) #define SPI_CR1_TX_CRC_NEXT (1 << 12) #define SPI_CR1_HW_CRC_EN (1 << 13) #define SPI_CR1_BIDIOE (1 << 14) #define SPI_CR2_SSOE (1 << 2) #define SPI_SR_RX_NOTEMPTY (1 << 0) #define SPI_SR_TX_EMPTY (1 << 1) #define SPI_SR_BUSY (1 << 7) /*** RCC ***/ #define RCC_CR_PLLRDY (1 << 25) #define RCC_CR_PLLON (1 << 24) #define RCC_CR_HSERDY (1 << 17) #define RCC_CR_HSEON (1 << 16) #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) #define RCC_CFGR_SW_HSI 0x0 #define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_PLL 0x2 #define RCC_PRESCALER_DIV_NONE 0 #define RCC_PRESCALER_DIV_2 8 #define RCC_PRESCALER_DIV_4 9 #define RCC_PLLCFGR_PLLSRC (1 << 22) #define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830)) #define GPIOA_AHB1_CLOCK_ER (1 << 0) #define GPIOB_AHB1_CLOCK_ER (1 << 1) #define GPIOC_AHB1_CLOCK_ER (1 << 2) #define GPIOD_AHB1_CLOCK_ER (1 << 3) #define GPIOE_AHB1_CLOCK_ER (1 << 4) #define GPIOA_BASE 0x40020000 #define GPIOB_BASE 0x40020400 #define GPIOC_BASE 0x40020800 #define GPIOD_BASE 0x40020C00 #define GPIOE_BASE 0x40021000 #define AHB2_CLOCK_ER (*(volatile uint32_t *)(0x40023834)) #define RNG_AHB2_CLOCK_ER (1 << 6) /* POWER CONTROL REGISTER */ #define POW_BASE (0x40007000) #define POW_CR (*(volatile uint32_t *)(POW_BASE + 0x00)) #define POW_SCR (*(volatile uint32_t *)(POW_BASE + 0x04)) #define POW_CR_VOS (1 << 14) #define POW_CR_FPDS (1 << 9) #define POW_CR_DPB (1 << 8) #define POW_CR_CSBF (1 << 3) #define POW_CR_CWUF (1 << 2) #define POW_CR_PDDS (1 << 1) #define POW_CR_LPDS (1 << 0) #define POW_SCR_BRE (1 << 9) #define POW_SCR_EWUP (1 << 4) #define POW_SCR_BRR (1 << 3) #define POW_SCR_WUF (1 << 0) /* GPIOS */ #define GPIOA_MODE (*(volatile uint32_t *)(GPIOA_BASE + 0x00)) #define GPIOA_AFL (*(volatile uint32_t *)(GPIOA_BASE + 0x20)) #define GPIOA_AFH (*(volatile uint32_t *)(GPIOA_BASE + 0x24)) #define GPIOA_OSPD (*(volatile uint32_t *)(GPIOA_BASE + 0x08)) #define GPIOA_PUPD (*(volatile uint32_t *)(GPIOA_BASE + 0x0c)) #define GPIOA_BSRR (*(volatile uint32_t *)(GPIOA_BASE + 0x18)) #define GPIOA_ODR (*(volatile uint32_t *)(GPIOA_BASE + 0x14)) #define GPIOA_IDR (*(volatile uint32_t *)(GPIOA_BASE + 0x10)) #define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00)) #define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20)) #define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24)) #define GPIOB_OSPD (*(volatile uint32_t *)(GPIOB_BASE + 0x08)) #define GPIOB_PUPD (*(volatile uint32_t *)(GPIOB_BASE + 0x0c)) #define GPIOB_BSRR (*(volatile uint32_t *)(GPIOB_BASE + 0x18)) #define GPIOB_ODR (*(volatile uint32_t *)(GPIOB_BASE + 0x14)) #define GPIOC_MODE (*(volatile uint32_t *)(GPIOC_BASE + 0x00)) #define GPIOC_OTYPE (*(volatile uint32_t *)(GPIOC_BASE + 0x04)) #define GPIOC_OSPEED (*(volatile uint32_t *)(GPIOC_BASE + 0x08)) #define GPIOC_AFL (*(volatile uint32_t *)(GPIOC_BASE + 0x20)) #define GPIOC_AFH (*(volatile uint32_t *)(GPIOC_BASE + 0x24)) #define GPIOC_OSPD (*(volatile uint32_t *)(GPIOC_BASE + 0x08)) #define GPIOC_PUPD (*(volatile uint32_t *)(GPIOC_BASE + 0x0c)) #define GPIOC_BSRR (*(volatile uint32_t *)(GPIOC_BASE + 0x18)) #define GPIOC_ODR (*(volatile uint32_t *)(GPIOC_BASE + 0x14)) #define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00)) #define GPIOD_OTYPE (*(volatile uint32_t *)(GPIOD_BASE + 0x04)) #define GPIOD_OSPEED (*(volatile uint32_t *)(GPIOD_BASE + 0x08)) #define GPIOD_AFL (*(volatile uint32_t *)(GPIOD_BASE + 0x20)) #define GPIOD_AFH (*(volatile uint32_t *)(GPIOD_BASE + 0x24)) #define GPIOD_OSPD (*(volatile uint32_t *)(GPIOD_BASE + 0x08)) #define GPIOD_PUPD (*(volatile uint32_t *)(GPIOD_BASE + 0x0c)) #define GPIOD_BSRR (*(volatile uint32_t *)(GPIOD_BASE + 0x18)) #define GPIOD_ODR (*(volatile uint32_t *)(GPIOD_BASE + 0x14)) #define GPIOE_MODE (*(volatile uint32_t *)(GPIOE_BASE + 0x00)) #define GPIOE_AFL (*(volatile uint32_t *)(GPIOE_BASE + 0x20)) #define GPIOE_AFH (*(volatile uint32_t *)(GPIOE_BASE + 0x24)) #define GPIOE_OSPD (*(volatile uint32_t *)(GPIOE_BASE + 0x08)) #define GPIOE_PUPD (*(volatile uint32_t *)(GPIOE_BASE + 0x0c)) #define GPIOE_BSRR (*(volatile uint32_t *)(GPIOE_BASE + 0x18)) #define GPIOE_ODR (*(volatile uint32_t *)(GPIOE_BASE + 0x14)) #define GPIO_MODE_AF (2) /* SDIO */ #define SDIO_BASE (0x40012C00) #define SDIO_POWER (*(volatile uint32_t *)((SDIO_BASE) + 0x00)) #define SDIO_CLKCR (*(volatile uint32_t *)((SDIO_BASE) + 0x04)) #define SDIO_ARG (*(volatile uint32_t *)((SDIO_BASE) + 0x08)) #define SDIO_CMD (*(volatile uint32_t *)((SDIO_BASE) + 0x0C)) #define SDIO_RESPCMD (*(volatile uint32_t *)((SDIO_BASE) + 0x10)) #define SDIO_RESP1 (*(volatile uint32_t *)((SDIO_BASE) + 0x14)) #define SDIO_RESP2 (*(volatile uint32_t *)((SDIO_BASE) + 0x18)) #define SDIO_RESP3 (*(volatile uint32_t *)((SDIO_BASE) + 0x1C)) #define SDIO_RESP4 (*(volatile uint32_t *)((SDIO_BASE) + 0x20)) #define SDIO_DTIMER (*(volatile uint32_t *)((SDIO_BASE) + 0x24)) #define SDIO_DLEN (*(volatile uint32_t *)((SDIO_BASE) + 0x28)) #define SDIO_DCTRL (*(volatile uint32_t *)((SDIO_BASE) + 0x2C)) #define SDIO_DCOUNT (*(volatile uint32_t *)((SDIO_BASE) + 0x30)) #define SDIO_STA (*(volatile uint32_t *)((SDIO_BASE) + 0x34)) #define SDIO_ICR (*(volatile uint32_t *)((SDIO_BASE) + 0x38)) #define SDIO_MASK (*(volatile uint32_t *)((SDIO_BASE) + 0x3C)) #define SDIO_FIFOCNT (*(volatile uint32_t *)((SDIO_BASE) + 0x48)) #define SDIO_FIFO (*(volatile uint32_t *)((SDIO_BASE) + 0x80)) #define SDIO_POWER_PWRCTRL_SHIFT 0 #define SDIO_POWER_PWRCTRL_PWROFF (0x0 << SDIO_POWER_PWRCTRL_SHIFT) #define SDIO_POWER_PWRCTRL_RSVPWRUP (0x2 << SDIO_POWER_PWRCTRL_SHIFT) #define SDIO_POWER_PWRCTRL_PWRON (0x3 << SDIO_POWER_PWRCTRL_SHIFT) #define SDIO_CLKCR_HWFC_EN (1 << 14) #define SDIO_CLKCR_NEGEDGE (1 << 13) #define SDIO_CLKCR_WIDBUS_SHIFT 11 #define SDIO_CLKCR_WIDBUS_1 (0x0 << SDIO_CLKCR_WIDBUS_SHIFT) #define SDIO_CLKCR_WIDBUS_4 (0x1 << SDIO_CLKCR_WIDBUS_SHIFT) #define SDIO_CLKCR_WIDBUS_8 (0x2 << SDIO_CLKCR_WIDBUS_SHIFT) #define SDIO_CLKCR_BYPASS (1 << 10) #define SDIO_CLKCR_PWRSAV (1 << 9) #define SDIO_CLKCR_CLKEN (1 << 8) #define SDIO_CLKCR_CLKDIV_SHIFT 0 #define SDIO_CLKCR_CLKDIV_MSK (0xFF << SDIO_CLKCR_CLKDIV_SHIFT) #define SDIO_CMD_ATACMD (1 << 14) #define SDIO_CMD_NIEN (1 << 13) #define SDIO_CMD_ENCMDCOMPL (1 << 12) #define SDIO_CMD_SDIOSUSPEND (1 << 11) #define SDIO_CMD_CPSMEN (1 << 10) #define SDIO_CMD_WAITPEND (1 << 9) #define SDIO_CMD_WAITINT (1 << 8) #define SDIO_CMD_WAITRESP_SHIFT 6 #define SDIO_CMD_WAITRESP_NO_0 (0x0 << SDIO_CMD_WAITRESP_SHIFT) #define SDIO_CMD_WAITRESP_SHORT (0x1 << SDIO_CMD_WAITRESP_SHIFT) #define SDIO_CMD_WAITRESP_NO_2 (0x2 << SDIO_CMD_WAITRESP_SHIFT) #define SDIO_CMD_WAITRESP_LONG (0x3 << SDIO_CMD_WAITRESP_SHIFT) #define SDIO_CMD_CMDINDEX_SHIFT 0 #define SDIO_CMD_CMDINDEX_MSK (0x3F << SDIO_CMD_CMDINDEX_SHIFT) #define SDIO_RESPCMD_SHIFT 0 #define SDIO_RESPCMD_MSK (0x3F << SDIO_RESPCMD_SHIFT) #define SDIO_DCTRL_SDIOEN (1 << 11) #define SDIO_DCTRL_RWMOD (1 << 10) #define SDIO_DCTRL_RWSTOP (1 << 9) #define SDIO_DCTRL_RWSTART (1 << 8) #define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_1 (0x1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_2 (0x2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_3 (0x3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_4 (0x4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_5 (0x5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_6 (0x6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_7 (0x7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_8 (0x8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_9 (0x9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_10 (0xA << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_11 (0xB << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_12 (0xC << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_13 (0xD << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_14 (0xE << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DMAEN (1 << 3) #define SDIO_DCTRL_DTMODE (1 << 2) #define SDIO_DCTRL_DTDIR (1 << 1) #define SDIO_DCTRL_DTEN (1 << 0) #define SDIO_STA_CEATAEND (1 << 23) #define SDIO_STA_SDIOIT (1 << 22) #define SDIO_STA_RXDAVL (1 << 21) #define SDIO_STA_TXDAVL (1 << 20) #define SDIO_STA_RXFIFOE (1 << 19) #define SDIO_STA_TXFIFOE (1 << 18) #define SDIO_STA_RXFIFOF (1 << 17) #define SDIO_STA_TXFIFOF (1 << 16) #define SDIO_STA_RXFIFOHF (1 << 15) #define SDIO_STA_TXFIFOHE (1 << 14) #define SDIO_STA_RXACT (1 << 13) #define SDIO_STA_TXACT (1 << 12) #define SDIO_STA_CMDACT (1 << 11) #define SDIO_STA_DBCKEND (1 << 10) #define SDIO_STA_STBITERR (1 << 9) #define SDIO_STA_DATAEND (1 << 8) #define SDIO_STA_CMDSENT (1 << 7) #define SDIO_STA_CMDREND (1 << 6) #define SDIO_STA_RXOVERR (1 << 5) #define SDIO_STA_TXUNDERR (1 << 4) #define SDIO_STA_DTIMEOUT (1 << 3) #define SDIO_STA_CTIMEOUT (1 << 2) #define SDIO_STA_DCRCFAIL (1 << 1) #define SDIO_STA_CCRCFAIL (1 << 0) #define SDIO_ICR_CEATAENDC (1 << 23) #define SDIO_ICR_SDIOITC (1 << 22) #define SDIO_ICR_DBCKENDC (1 << 10) #define SDIO_ICR_STBITERRC (1 << 9) #define SDIO_ICR_DATAENDC (1 << 8) #define SDIO_ICR_CMDSENTC (1 << 7) #define SDIO_ICR_CMDRENDC (1 << 6) #define SDIO_ICR_RXOVERRC (1 << 5) #define SDIO_ICR_TXUNDERRC (1 << 4) #define SDIO_ICR_DTIMEOUTC (1 << 3) #define SDIO_ICR_CTIMEOUTC (1 << 2) #define SDIO_ICR_DCRCFAILC (1 << 1) #define SDIO_ICR_CCRCFAILC (1 << 0) #define SDIO_MASK_CEATAENDIE (1 << 23) #define SDIO_MASK_SDIOITIE (1 << 22) #define SDIO_MASK_RXDAVLIE (1 << 21) #define SDIO_MASK_TXDAVLIE (1 << 20) #define SDIO_MASK_RXFIFOEIE (1 << 19) #define SDIO_MASK_TXFIFOEIE (1 << 18) #define SDIO_MASK_RXFIFOFIE (1 << 17) #define SDIO_MASK_TXFIFOFIE (1 << 16) #define SDIO_MASK_RXFIFOHFIE (1 << 15) #define SDIO_MASK_TXFIFOHEIE (1 << 14) #define SDIO_MASK_RXACTIE (1 << 13) #define SDIO_MASK_TXACTIE (1 << 12) #define SDIO_MASK_CMDACTIE (1 << 11) #define SDIO_MASK_DBCKENDIE (1 << 10) #define SDIO_MASK_STBITERRIE (1 << 9) #define SDIO_MASK_DATAENDIE (1 << 8) #define SDIO_MASK_CMDSENTIE (1 << 7) #define SDIO_MASK_CMDRENDIE (1 << 6) #define SDIO_MASK_RXOVERRIE (1 << 5) #define SDIO_MASK_TXUNDERRIE (1 << 4) #define SDIO_MASK_DTIMEOUTIE (1 << 3) #define SDIO_MASK_CTIMEOUTIE (1 << 2) #define SDIO_MASK_DCRCFAILIE (1 << 1) #define SDIO_MASK_CCRCFAILIE (1 << 0) /* Timers */ #define TIM2_BASE (0x40000000) #define TIM2_CR1 (*(volatile uint32_t *)(TIM2_BASE + 0x00)) #define TIM2_DIER (*(volatile uint32_t *)(TIM2_BASE + 0x0c)) #define TIM2_SR (*(volatile uint32_t *)(TIM2_BASE + 0x10)) #define TIM2_CNT (*(volatile uint32_t *)(TIM2_BASE + 0x24)) #define TIM2_PSC (*(volatile uint32_t *)(TIM2_BASE + 0x28)) #define TIM2_ARR (*(volatile uint32_t *)(TIM2_BASE + 0x2c)) #define TIM4_BASE (0x40000800) #define TIM4_CR1 (*(volatile uint32_t *)(TIM4_BASE + 0x00)) #define TIM4_DIER (*(volatile uint32_t *)(TIM4_BASE + 0x0c)) #define TIM4_SR (*(volatile uint32_t *)(TIM4_BASE + 0x10)) #define TIM4_CCMR1 (*(volatile uint32_t *)(TIM4_BASE + 0x18)) #define TIM4_CCMR2 (*(volatile uint32_t *)(TIM4_BASE + 0x1c)) #define TIM4_CCER (*(volatile uint32_t *)(TIM4_BASE + 0x20)) #define TIM4_PSC (*(volatile uint32_t *)(TIM4_BASE + 0x28)) #define TIM4_ARR (*(volatile uint32_t *)(TIM4_BASE + 0x2c)) #define TIM4_CCR4 (*(volatile uint32_t *)(TIM4_BASE + 0x40)) #define TIM_DIER_UIE (1 << 0) #define TIM_SR_UIF (1 << 0) #define TIM_CR1_CLOCK_ENABLE (1 << 0) #define TIM_CR1_UPD_RS (1 << 2) #define TIM_CR1_ARPE (1 << 7) #define TIM_CCER_CC4_ENABLE (1 << 12) #define TIM_CCMR1_OC1M_PWM1 (0x06 << 4) #define TIM_CCMR2_OC4M_PWM1 (0x06 << 12) #define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830)) #define GPIOD_AHB1_CLOCK_ER (1 << 3) #define GPIOD_BASE 0x40020c00 #define GPIOD_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00)) #define GPIOD_OTYPE (*(volatile uint32_t *)(GPIOD_BASE + 0x04)) #define GPIOD_PUPD (*(volatile uint32_t *)(GPIOD_BASE + 0x0c)) #define GPIOD_ODR (*(volatile uint32_t *)(GPIOD_BASE + 0x14)) /* ADC */ #define ADC1_BASE (0x40012000) #define ADC_COM_BASE (0x40012300) #define ADC_COM_CCR (*(volatile uint32_t *)(ADC_COM_BASE + 0x04)) #define ADC1_SR (*(volatile uint32_t *)(ADC1_BASE + 0x00)) #define ADC1_CR1 (*(volatile uint32_t *)(ADC1_BASE + 0x04)) #define ADC1_CR2 (*(volatile uint32_t *)(ADC1_BASE + 0x08)) #define ADC1_SMPR1 (*(volatile uint32_t *)(ADC1_BASE + 0x0c)) #define ADC1_SMPR2 (*(volatile uint32_t *)(ADC1_BASE + 0x10)) #define ADC1_SQR3 (*(volatile uint32_t *)(ADC1_BASE + 0x34)) #define ADC1_DR (*(volatile uint32_t *)(ADC1_BASE + 0x4c)) #define ADC_CR1_SCAN (1 << 8) #define ADC_CR2_EN (1 << 0) #define ADC_CR2_CONT (1 << 1) #define ADC_CR2_SWSTART (1 << 30) #define ADC_SR_EOC (1 << 1) #define ADC_SMPR_SMP_480CYC (0x7) /* Reboot */ #define AIRCR *(volatile uint32_t *)(0xE000ED0C) #define AIRCR_VKEY (0x05FA << 16) # define AIRCR_SYSRESETREQ (1 << 2) static inline void reboot(void) { AIRCR = AIRCR_SYSRESETREQ | AIRCR_VKEY; } #endif