startup.c 6.4 KB

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  1. /*
  2. * (c) danielinux 2019
  3. *
  4. * GPLv.2
  5. *
  6. * See LICENSE for details
  7. */
  8. extern unsigned int _stored_data;
  9. extern unsigned int _start_data;
  10. extern unsigned int _end_data;
  11. extern unsigned int _start_bss;
  12. extern unsigned int _end_bss;
  13. extern unsigned int _end_stack;
  14. extern unsigned int _start_heap;
  15. #define STACK_PAINTING
  16. static volatile unsigned int avail_mem = 0;
  17. static unsigned int sp;
  18. extern void main(void);
  19. extern void isr_exti_rot0(void);
  20. extern void isr_exti_rot1(void);
  21. extern void isr_exti_channel(void);
  22. extern void isr_exti_button(void);
  23. extern void isr_tim2(void);
  24. extern void isr_systick(void);
  25. extern void otg_fs_isr(void);
  26. extern void usb_fs_wkup_isr(void);
  27. void isr_reset(void) {
  28. register unsigned int *src, *dst;
  29. src = (unsigned int *) &_stored_data;
  30. dst = (unsigned int *) &_start_data;
  31. /* Copy the .data section from flash to RAM. */
  32. while (dst < (unsigned int *)&_end_data) {
  33. *dst = *src;
  34. dst++;
  35. src++;
  36. }
  37. /* Initialize the BSS section to 0 */
  38. dst = &_start_bss;
  39. while (dst < (unsigned int *)&_end_bss) {
  40. *dst = 0U;
  41. dst++;
  42. }
  43. /* Paint the stack. */
  44. avail_mem = &_end_stack - &_start_heap;
  45. #ifdef STACK_PAINTING
  46. {
  47. asm volatile("mrs %0, msp" : "=r"(sp));
  48. dst = ((unsigned int *)(&_end_stack)) - (8192 / sizeof(unsigned int)); ;
  49. while ((unsigned int)dst < sp) {
  50. *dst = 0xDEADC0DE;
  51. dst++;
  52. }
  53. }
  54. #endif
  55. /* Run the program! */
  56. main();
  57. }
  58. void isr_fault(void)
  59. {
  60. /* Panic. */
  61. while(1) ;;
  62. }
  63. void isr_memfault(void)
  64. {
  65. /* Panic. */
  66. while(1) ;;
  67. }
  68. void isr_busfault(void)
  69. {
  70. /* Panic. */
  71. while(1) ;;
  72. }
  73. void isr_usagefault(void)
  74. {
  75. /* Panic. */
  76. while(1) ;;
  77. }
  78. void isr_empty(void)
  79. {
  80. /* Ignore the event and continue */
  81. }
  82. __attribute__ ((section(".isr_vector")))
  83. void (* const IV[])(void) =
  84. {
  85. (void (*)(void))(&_end_stack),
  86. isr_reset, // Reset
  87. isr_fault, // NMI
  88. isr_fault, // HardFault
  89. isr_memfault, // MemFault
  90. isr_busfault, // BusFault
  91. isr_usagefault, // UsageFault
  92. 0, 0, 0, 0, // 4x reserved
  93. isr_empty, // SVC
  94. isr_empty, // DebugMonitor
  95. 0, // reserved
  96. isr_empty, // PendSV
  97. isr_systick, // SysTick
  98. isr_empty, // NVIC_WWDG_IRQ 0
  99. isr_empty, // PVD_IRQ 1
  100. isr_empty, // TAMP_STAMP_IRQ 2
  101. isr_empty, // RTC_WKUP_IRQ 3
  102. isr_empty, // FLASH_IRQ 4
  103. isr_empty, // RCC_IRQ 5
  104. isr_exti_button, // EXTI0_IRQ 6
  105. isr_empty, // EXTI1_IRQ 7
  106. isr_empty, // EXTI2_IRQ 8
  107. isr_empty, // EXTI3_IRQ 9
  108. isr_exti_rot1, // EXTI4_IRQ 10
  109. isr_empty, // DMA1_STREAM0_IRQ 11
  110. isr_empty, // DMA1_STREAM1_IRQ 12
  111. isr_empty, // DMA1_STREAM2_IRQ 13
  112. isr_empty, // DMA1_STREAM3_IRQ 14
  113. isr_empty, // DMA1_STREAM4_IRQ 15
  114. isr_empty, // DMA1_STREAM5_IRQ 16
  115. isr_empty, // DMA1_STREAM6_IRQ 17
  116. isr_empty, // ADC_IRQ 18
  117. isr_empty, // CAN1_TX_IRQ 19
  118. isr_empty, // CAN1_RX0_IRQ 20
  119. isr_empty, // CAN1_RX1_IRQ 21
  120. isr_empty, // CAN1_SCE_IRQ 22
  121. isr_exti_channel, // EXTI9_5_IRQ 23
  122. isr_empty, // TIM1_BRK_TIM9_IRQ 24
  123. isr_empty, // TIM1_UP_TIM10_IRQ 25
  124. isr_empty, // TIM1_TRG_COM_TIM11_IRQ 26
  125. isr_empty, // TIM1_CC_IRQ 27
  126. isr_tim2, // TIM2_IRQ 28
  127. isr_empty, // TIM3_IRQ 29
  128. isr_empty, // TIM4_IRQ 30
  129. isr_empty, // I2C1_EV_IRQ 31
  130. isr_empty, // I2C1_ER_IRQ 32
  131. isr_empty, // I2C2_EV_IRQ 33
  132. isr_empty, // I2C2_ER_IRQ 34
  133. isr_empty, // SPI1_IRQ 35
  134. isr_empty, // SPI2_IRQ 36
  135. isr_empty, // USART1_IRQ 37
  136. isr_empty, // USART2_IRQ 38
  137. isr_empty, // USART3_IRQ 39
  138. isr_exti_rot0, // EXTI15_10_IRQ 40
  139. isr_empty, // RTC_ALARM_IRQ 41
  140. usb_fs_wkup_isr, // USB_FS_WKUP_IRQ 42
  141. isr_empty, // TIM8_BRK_TIM12_IRQ 43
  142. isr_empty, // TIM8_UP_TIM13_IRQ 44
  143. isr_empty, // TIM8_TRG_COM_TIM14_IRQ 45
  144. isr_empty, // TIM8_CC_IRQ 46
  145. isr_empty, // DMA1_STREAM7_IRQ 47
  146. isr_empty, // FSMC_IRQ
  147. isr_empty, // SDIO_IRQ
  148. isr_empty, // TIM5_IRQ
  149. isr_empty, // SPI3_IRQ
  150. isr_empty, // UART4_IRQ
  151. isr_empty, // UART5_IRQ
  152. isr_empty, // TIM6_DAC_IRQ
  153. isr_empty, // TIM7_IRQ
  154. isr_empty, // DMA2_STREAM0_IRQ
  155. isr_empty, // DMA2_STREAM1_IRQ
  156. isr_empty, // DMA2_STREAM2_IRQ
  157. isr_empty, // DMA2_STREAM3_IRQ
  158. isr_empty, // DMA2_STREAM4_IRQ
  159. isr_empty, // ETH_IRQ
  160. isr_empty, // ETH_WKUP_IRQ
  161. isr_empty, // CAN2_TX_IRQ
  162. isr_empty, // CAN2_RX0_IRQ
  163. isr_empty, // CAN2_RX1_IRQ
  164. isr_empty, // CAN2_SCE_IRQ
  165. otg_fs_isr, // OTG_FS_IRQ
  166. isr_empty, // DMA2_STREAM5_IRQ
  167. isr_empty, // DMA2_STREAM6_IRQ
  168. isr_empty, // DMA2_STREAM7_IRQ
  169. isr_empty, // USART6_IRQ
  170. isr_empty, // I2C3_EV_IRQ
  171. isr_empty, // I2C3_ER_IRQ
  172. isr_empty, // OTG_HS_EP1_OUT_IRQ
  173. isr_empty, // OTG_HS_EP1_IN_IRQ
  174. isr_empty, // OTG_HS_WKUP_IRQ
  175. isr_empty, // OTG_HS_IRQ
  176. isr_empty, // DCMI_IRQ
  177. isr_empty, // CRYP_IRQ
  178. isr_empty, // HASH_RNG_IRQ
  179. isr_empty, // FPU_IRQ
  180. isr_empty, // UART7_IRQ
  181. isr_empty, // UART8_IRQ
  182. isr_empty, // SPI4_IRQ
  183. isr_empty, // SPI5_IRQ
  184. isr_empty, // SPI6_IRQ
  185. isr_empty, // SAI1_IRQ
  186. isr_empty, // LCD_TFT_IRQ
  187. isr_empty, // LCD_TFT_ERR_IRQ
  188. isr_empty, // DMA2D_IRQ
  189. };