system.c 4.0 KB

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  1. /*
  2. * (c) danielinux 2019
  3. *
  4. * GPLv.2
  5. *
  6. * See LICENSE for details
  7. */
  8. #include <stdint.h>
  9. #include "system.h"
  10. uint32_t cpu_freq = 84000000;
  11. /*** FLASH ***/
  12. #define FLASH_BASE (0x40023C00)
  13. #define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
  14. #define FLASH_ACR_ENABLE_DATA_CACHE (1 << 10)
  15. #define FLASH_ACR_ENABLE_INST_CACHE (1 << 9)
  16. static void flash_set_waitstates(int waitstates)
  17. {
  18. FLASH_ACR |= waitstates | FLASH_ACR_ENABLE_DATA_CACHE | FLASH_ACR_ENABLE_INST_CACHE;
  19. }
  20. /*** RCC ***/
  21. #define RCC_BASE (0x40023800)
  22. #define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00))
  23. #define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x04))
  24. #define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08))
  25. #define RCC_CR_PLLRDY (1 << 25)
  26. #define RCC_CR_PLLON (1 << 24)
  27. #define RCC_CR_HSERDY (1 << 17)
  28. #define RCC_CR_HSEON (1 << 16)
  29. #define RCC_CR_HSIRDY (1 << 1)
  30. #define RCC_CR_HSION (1 << 0)
  31. #define RCC_CFGR_SW_HSI 0x0
  32. #define RCC_CFGR_SW_HSE 0x1
  33. #define RCC_CFGR_SW_PLL 0x2
  34. #define RCC_PLLCFGR_PLLSRC (1 << 22)
  35. #define RCC_PRESCALER_DIV_NONE 0
  36. #define RCC_PRESCALER_DIV_2 8
  37. #define RCC_PRESCALER_DIV_4 9
  38. void clock_pll_off(void)
  39. {
  40. uint32_t reg32;
  41. /* Enable internal high-speed oscillator. */
  42. RCC_CR |= RCC_CR_HSION;
  43. DMB();
  44. while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
  45. /* Select HSI as SYSCLK source. */
  46. reg32 = RCC_CFGR;
  47. reg32 &= ~((1 << 1) | (1 << 0));
  48. RCC_CFGR = (reg32 | RCC_CFGR_SW_HSI);
  49. DMB();
  50. /* Turn off PLL */
  51. RCC_CR &= ~RCC_CR_PLLON;
  52. DMB();
  53. }
  54. void clock_pll_on(void)
  55. {
  56. uint32_t reg32;
  57. uint32_t plln, pllm, pllq, pllp, pllr, hpre, ppre1, ppre2, flash_waitstates;
  58. /* Enable Power controller */
  59. APB1_CLOCK_ER |= PWR_APB1_CLOCK_ER_VAL;
  60. /* Select clock parameters */
  61. pllm = 8;
  62. plln = 336;
  63. pllp = 4;
  64. pllq = 7;
  65. pllr = 0;
  66. hpre = RCC_PRESCALER_DIV_NONE;
  67. ppre1 = RCC_PRESCALER_DIV_2;
  68. ppre2 = RCC_PRESCALER_DIV_NONE;
  69. flash_waitstates = 2;
  70. flash_set_waitstates(flash_waitstates);
  71. /* Enable internal high-speed oscillator. */
  72. RCC_CR |= RCC_CR_HSION;
  73. DMB();
  74. while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
  75. /* Select HSI as SYSCLK source. */
  76. reg32 = RCC_CFGR;
  77. reg32 &= ~((1 << 1) | (1 << 0));
  78. RCC_CFGR = (reg32 | RCC_CFGR_SW_HSI);
  79. DMB();
  80. /* Enable external high-speed oscillator 12MHz. */
  81. RCC_CR |= RCC_CR_HSEON;
  82. DMB();
  83. while ((RCC_CR & RCC_CR_HSERDY) == 0) {};
  84. /*
  85. * Set prescalers for AHB, ADC, ABP1, ABP2.
  86. */
  87. reg32 = RCC_CFGR;
  88. reg32 &= ~(0xF0);
  89. RCC_CFGR = (reg32 | (hpre << 4));
  90. DMB();
  91. reg32 = RCC_CFGR;
  92. reg32 &= ~(0x1C00);
  93. RCC_CFGR = (reg32 | (ppre1 << 10));
  94. DMB();
  95. reg32 = RCC_CFGR;
  96. reg32 &= ~(0x07 << 13);
  97. RCC_CFGR = (reg32 | (ppre2 << 13));
  98. DMB();
  99. /* Set PLL config */
  100. reg32 = RCC_PLLCFGR;
  101. reg32 &= ~(PLL_FULL_MASK);
  102. RCC_PLLCFGR = reg32 | RCC_PLLCFGR_PLLSRC | pllm |
  103. (plln << 6) | (((pllp >> 1) - 1) << 16) |
  104. (pllq << 24);
  105. DMB();
  106. /* Enable PLL oscillator and wait for it to stabilize. */
  107. RCC_CR |= RCC_CR_PLLON;
  108. DMB();
  109. while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
  110. /* Select PLL as SYSCLK source. */
  111. reg32 = RCC_CFGR;
  112. reg32 &= ~((1 << 1) | (1 << 0));
  113. RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
  114. DMB();
  115. /* Wait for PLL clock to be selected. */
  116. while (((RCC_CFGR & ((1 << 3) | (1 << 2))) >> 2) != RCC_CFGR_SW_PLL) {};
  117. /* Disable internal high-speed oscillator. */
  118. RCC_CR &= ~RCC_CR_HSION;
  119. }
  120. void *__attribute__((weak)) memcpy(void *d, void *s, uint32_t len)
  121. {
  122. uint32_t *src, *dst;
  123. uint8_t *sb, *db;
  124. src = s;
  125. dst = d;
  126. while(len > 3) {
  127. *(dst++) = *(src++);
  128. len -= 4;
  129. }
  130. sb = (uint8_t *)src;
  131. db = (uint8_t *)dst;
  132. while(len > 0) {
  133. *(db++) = *(sb++);
  134. len--;
  135. }
  136. return d;
  137. }
  138. void panic(void)
  139. {
  140. printf("PANIC!");
  141. while(1)
  142. ;
  143. }