173 líneas
5,4 KiB
C
173 líneas
5,4 KiB
C
/*
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*
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* MIT License
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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extern unsigned int _stored_data;
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extern unsigned int _start_data;
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extern unsigned int _end_data;
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extern unsigned int _start_bss;
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extern unsigned int _end_bss;
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extern unsigned int _end_stack;
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extern unsigned int _start_heap;
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extern void isr_uart3(void);
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#define STACK_PAINTING
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static volatile unsigned int avail_mem = 0;
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static unsigned int sp;
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extern void main(void);
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void isr_reset(void) {
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register unsigned int *src, *dst;
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src = (unsigned int *) &_stored_data;
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dst = (unsigned int *) &_start_data;
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/* Copy the .data section from flash to RAM. */
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while (dst < (unsigned int *)&_end_data) {
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*dst = *src;
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dst++;
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src++;
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}
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/* Initialize the BSS section to 0 */
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dst = &_start_bss;
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while (dst < (unsigned int *)&_end_bss) {
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*dst = 0U;
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dst++;
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}
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/* Paint the stack. */
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avail_mem = &_end_stack - &_start_heap;
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#ifdef STACK_PAINTING
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{
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asm volatile("mrs %0, msp" : "=r"(sp));
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dst = ((unsigned int *)(&_end_stack)) - (8192 / sizeof(unsigned int)); ;
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while ((unsigned int)dst < sp) {
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*dst = 0xDEADC0DE;
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dst++;
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}
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}
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#endif
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/* Run the program! */
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main();
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}
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void isr_fault(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_memfault(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_busfault(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_usagefault(void)
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{
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/* Panic. */
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while(1) ;;
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}
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void isr_empty(void)
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{
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/* Ignore the event and continue */
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}
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__attribute__ ((section(".isr_vector")))
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void (* const IV[])(void) =
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{
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(void (*)(void))(&_end_stack),
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isr_reset, // Reset
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isr_fault, // NMI
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isr_fault, // HardFault
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isr_memfault, // MemFault
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isr_busfault, // BusFault
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isr_usagefault, // UsageFault
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0, 0, 0, 0, // 4x reserved
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isr_empty, // SVC
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isr_empty, // DebugMonitor
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0, // reserved
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isr_empty, // PendSV
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isr_empty, // SysTick
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isr_empty, // NVIC_WWDG_IRQ 0
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isr_empty, // PVD_IRQ 1
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isr_empty, // TAMP_STAMP_IRQ 2
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isr_empty, // RTC_WKUP_IRQ 3
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isr_empty, // FLASH_IRQ 4
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isr_empty, // RCC_IRQ 5
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isr_empty, // EXTI0_IRQ 6
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isr_empty, // EXTI1_IRQ 7
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isr_empty, // EXTI2_IRQ 8
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isr_empty, // EXTI3_IRQ 9
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isr_empty, // EXTI4_IRQ 10
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isr_empty, // DMA1_STREAM0_IRQ 11
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isr_empty, // DMA1_STREAM1_IRQ 12
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isr_empty, // DMA1_STREAM2_IRQ 13
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isr_empty, // DMA1_STREAM3_IRQ 14
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isr_empty, // DMA1_STREAM4_IRQ 15
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isr_empty, // DMA1_STREAM5_IRQ 16
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isr_empty, // DMA1_STREAM6_IRQ 17
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isr_empty, // ADC_IRQ 18
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isr_empty, // CAN1_TX_IRQ 19
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isr_empty, // CAN1_RX0_IRQ 20
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isr_empty, // CAN1_RX1_IRQ 21
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isr_empty, // CAN1_SCE_IRQ 22
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isr_empty, // EXTI9_5_IRQ 23
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isr_empty, // TIM1_BRK_TIM9_IRQ 24
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isr_empty, // TIM1_UP_TIM10_IRQ 25
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isr_empty, // TIM1_TRG_COM_TIM11_IRQ 26
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isr_empty, // TIM1_CC_IRQ 27
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isr_empty, // TIM2_IRQ 28
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isr_empty, // TIM3_IRQ 29
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isr_empty, // TIM4_IRQ 30
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isr_empty, // I2C1_EV_IRQ 31
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isr_empty, // I2C1_ER_IRQ 32
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isr_empty, // I2C2_EV_IRQ 33
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isr_empty, // I2C2_ER_IRQ 34
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isr_empty, // SPI1_IRQ 35
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isr_empty, // SPI2_IRQ 36
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isr_empty, // USART1_IRQ 37
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isr_empty, // USART2_IRQ 38
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isr_empty, // USART3_IRQ 39
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isr_empty, // EXTI15_10_IRQ 40
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isr_empty, // RTC_ALARM_IRQ 41
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isr_empty, // USB_FS_WKUP_IRQ 42
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isr_empty, // TIM8_BRK_TIM12_IRQ 43
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isr_empty, // TIM8_UP_TIM13_IRQ 44
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isr_empty, // TIM8_TRG_COM_TIM14_IRQ 45
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isr_empty, // TIM8_CC_IRQ 46
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isr_empty, // DMA1_STREAM7_IRQ 47
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};
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