Merge branch 'add-template-content' into 'main'

Add template content

See merge request atopile/atopile-project-template!1

.gitignore

@@ -0,0 +1,32 @@
+# For PCBs designed using KiCad: https://www.kicad.org/
+# Format documentation: https://kicad.org/help/file-formats/
+
+# Temporary files
+*.000
+*.bak
+*.bck
+*.kicad_pcb-bak
+*.kicad_sch-bak
+*-backups
+*.kicad_prl
+*.sch-bak
+*~
+_autosave-*
+*.tmp
+*-save.pro
+*-save.kicad_pcb
+fp-info-cache
+
+# Netlist files (exported from Eeschema)
+*.net
+
+# Autorouter files (exported from Pcbnew)
+*.dsn
+*.ses
+
+# Exported BOM files
+*.xml
+*.csv
+
+build/
+.DS_Store

.gitlab-ci.yml

@@ -0,0 +1,54 @@
+stages:
+  - check
+  - build
+  - store
+
+check-ato:
+  stage: check
+  image: registry.atopile.io/atopile/atopile-dev:latest
+  script:
+    - ato check elec/src
+
+build-gerbers-default:
+  stage: build
+  image:
+    name: kicad/kicad:nightly
+    pull_policy: if-not-present
+  script:
+    - mkdir -p build/default/src
+    - cd build/default
+    - cp ../../elec/layout/*.kicad_pcb src/
+    - sed -i "s/"'{{GITHASH}}'"/$CI_COMMIT_SHORT_SHA/g" src/*.kicad_pcb
+    - mkdir gerbers
+    - kicad-cli pcb export gerbers -o gerbers/ src/*.kicad_pcb
+    - kicad-cli pcb export drill -o gerbers/ src/*.kicad_pcb
+    - zip "gerbers-$CI_COMMIT_SHORT_SHA.zip" gerbers/*
+
+    # position files need some massaging for JLCPCB
+    - kicad-cli pcb export pos --format csv --units mm --use-drill-file-origin -o servo-drive-pos.csv src/*.kicad_pcb
+    - POS_HEADER="$(cat ../../metadata/pos-header)"
+    - sed -i "1s/.*/$POS_HEADER/" servo-drive-pos.csv
+
+    # Export step file
+    - kicad-cli pcb export step --subst-models -o board_3d_shape.step src/*.kicad_pcb
+  artifacts:
+    paths:
+      - build/
+
+build-ato-default:
+  stage: build
+  image: registry.atopile.io/atopile/atopile-dev:latest
+  script:
+    - ato build elec/src
+  artifacts:
+    paths:
+      - build/
+
+store-build:
+  stage: store
+  image: alpine
+  script:
+    - echo "noop"
+  artifacts:
+    paths:
+      - build/

README.md

@@ -1,4 +1,4 @@
-# Atopile Project Template
+# atopile Project Template
 
 This project can be used as a starting template for an atopile project. This template provides the following aspects:
 
@@ -7,9 +7,15 @@ This project can be used as a starting template for an atopile project. This tem
 - A gitlab CI file to generate your artifacts automatically
 - A gitignore file with the relevant files extensions to be ignored in the repository
 
+## How to build
+
+1. Install atopile following the documentation below
+2. Run `ato build elec/src`
+3. Load the netlist into your kicad pcb layout
+
 ## Documentation
 
-The documentaton for the project can be found at http://docs.atopile.io
+The documentation for the project can be found at http://docs.atopile.io
 
 ## Example projects
 

elec/layout/atopile-project-template.kicad_pcb

@@ -0,0 +1,203 @@
+(kicad_pcb (version 20221018) (generator pcbnew)
+
+  (general
+    (thickness 1.6)
+  )
+
+  (paper "A4")
+  (layers
+    (0 "F.Cu" signal)
+    (31 "B.Cu" signal)
+    (32 "B.Adhes" user "B.Adhesive")
+    (33 "F.Adhes" user "F.Adhesive")
+    (34 "B.Paste" user)
+    (35 "F.Paste" user)
+    (36 "B.SilkS" user "B.Silkscreen")
+    (37 "F.SilkS" user "F.Silkscreen")
+    (38 "B.Mask" user)
+    (39 "F.Mask" user)
+    (40 "Dwgs.User" user "User.Drawings")
+    (41 "Cmts.User" user "User.Comments")
+    (42 "Eco1.User" user "User.Eco1")
+    (43 "Eco2.User" user "User.Eco2")
+    (44 "Edge.Cuts" user)
+    (45 "Margin" user)
+    (46 "B.CrtYd" user "B.Courtyard")
+    (47 "F.CrtYd" user "F.Courtyard")
+    (48 "B.Fab" user)
+    (49 "F.Fab" user)
+    (50 "User.1" user)
+    (51 "User.2" user)
+    (52 "User.3" user)
+    (53 "User.4" user)
+    (54 "User.5" user)
+    (55 "User.6" user)
+    (56 "User.7" user)
+    (57 "User.8" user)
+    (58 "User.9" user)
+  )
+
+  (setup
+    (pad_to_mask_clearance 0)
+    (pcbplotparams
+      (layerselection 0x00010fc_ffffffff)
+      (plot_on_all_layers_selection 0x0000000_00000000)
+      (disableapertmacros false)
+      (usegerberextensions false)
+      (usegerberattributes true)
+      (usegerberadvancedattributes true)
+      (creategerberjobfile true)
+      (dashed_line_dash_ratio 12.000000)
+      (dashed_line_gap_ratio 3.000000)
+      (svgprecision 4)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (dxfpolygonmode true)
+      (dxfimperialunits true)
+      (dxfusepcbnewfont true)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (sketchpadsonfab false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory "")
+    )
+  )
+
+  (net 0 "")
+  (net 1 "HelloWorld-vcc_5v")
+  (net 2 "HelloWorld-gnd")
+  (net 3 "timer-trigger")
+  (net 4 "timer-output")
+  (net 5 "timer-reset")
+  (net 6 "timer-ctrl_v")
+  (net 7 "timer-threshold")
+  (net 8 "timer-discharge")
+
+  (footprint "lib:DIP-8_L9.7-W6.4-P2.54-LS7.6-BL" (layer "F.Cu")
+    (tstamp a2e90237-fe77-4995-b261-fc2b9c1522d2)
+    (at 142.24 93.98)
+    (path "/546edf20-be40-6bfe-8c94-ffc9723636c7/e196c9c9-3d04-2b38-edae-8002d8fbee81")
+    (attr smd)
+    (fp_text reference "U1" (at 6.363769 -1.989911) (layer "F.SilkS")
+        (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 2a632482-dc67-4760-b2a8-03c8697d1748)
+    )
+    (fp_text value "" (at 0 7.81) (layer "F.Fab")
+        (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 7a5cb92a-40dd-4685-b74e-d399d1e63701)
+    )
+    (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
+        (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp a838f80d-773f-46c5-98cd-9b03ab9a9886)
+    )
+    (fp_line (start -5.08 -2.53) (end 5.08 -2.53)
+      (stroke (width 0.25) (type solid)) (layer "F.SilkS") (tstamp ecc26f25-012b-45ee-a3aa-12ceedc3d65d))
+    (fp_line (start -5.08 -0.76) (end -5.08 -2.53)
+      (stroke (width 0.25) (type solid)) (layer "F.SilkS") (tstamp fe7c4c01-6d51-4edb-84c8-2dec903f67db))
+    (fp_line (start -5.08 2.54) (end -5.08 0.77)
+      (stroke (width 0.25) (type solid)) (layer "F.SilkS") (tstamp ab02cd32-e59a-4099-b4c5-0bfd69f12b79))
+    (fp_line (start -5.08 2.54) (end 5.08 2.54)
+      (stroke (width 0.25) (type solid)) (layer "F.SilkS") (tstamp 5dd72741-ed6a-4a50-b46c-1a1afcf64de8))
+    (fp_line (start 5.08 2.54) (end 5.08 -2.53)
+      (stroke (width 0.25) (type solid)) (layer "F.SilkS") (tstamp 362c743c-a26a-464b-b78c-23b916088736))
+    (fp_arc (start -5.093438 0.769883) (mid -5.073281 -0.769971) (end -5.08 0.77)
+      (stroke (width 0.25) (type solid)) (layer "F.SilkS") (tstamp 9abbc5ef-d3dc-4257-889c-b41a96471954))
+    (fp_circle (center -3.94 4.45) (end -3.64 4.45)
+      (stroke (width 0.6) (type solid)) (fill none) (layer "Cmts.User") (tstamp 4e4e75c9-526d-49f3-8053-84a777ad499c))
+    (fp_circle (center -4.83 3.94) (end -4.8 3.94)
+      (stroke (width 0.06) (type solid)) (fill none) (layer "F.Fab") (tstamp 5807565d-2a8b-450e-8879-9380f5e3791c))
+    (pad "1" thru_hole rect (at -3.81 3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 2 "HelloWorld-gnd") (tstamp 0ed40330-bc43-434d-92ed-dde9ae664c44))
+    (pad "2" thru_hole circle (at -1.27 3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 3 "timer-trigger") (tstamp c24c91b1-2cea-4e40-874f-8cc9ad880dc0))
+    (pad "3" thru_hole circle (at 1.27 3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 4 "timer-output") (tstamp 905153df-5fa9-4f4b-994f-4c6615fb8a48))
+    (pad "4" thru_hole circle (at 3.81 3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 5 "timer-reset") (tstamp df1c5b80-5c30-4985-ba66-363857358857))
+    (pad "5" thru_hole circle (at 3.81 -3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 6 "timer-ctrl_v") (tstamp 04352a39-87a1-418e-8749-37bea2c74924))
+    (pad "6" thru_hole circle (at 1.27 -3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 7 "timer-threshold") (tstamp 92d84c01-7503-4b96-92fe-9bea459f0f60))
+    (pad "7" thru_hole circle (at -1.27 -3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 8 "timer-discharge") (tstamp 92f8caf8-8c56-4a20-b86c-73800f927173))
+    (pad "8" thru_hole circle (at -3.81 -3.81) (size 1.8 1.8) (drill 0.999998) (layers "*.Cu" "*.Mask")
+      (net 1 "HelloWorld-vcc_5v") (tstamp 3a37fd1a-c6d1-492f-a754-501865f123c5))
+    (model "./lib/lib.3dshapes/DIP-8_L9.8-W6.6-H3.5-LS7.62-P2.54.wrl"
+      (offset (xyz 0 -0 3))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu")
+    (tstamp ce2f74d7-ced1-4b84-99de-3aa7550e8912)
+    (at 133.991711 94.410054 -90)
+    (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+    (tags "capacitor")
+    (path "/546edf20-be40-6bfe-8c94-ffc9723636c7/dfb357ea-4a2f-3c10-f408-df92fdd242fb")
+    (attr smd)
+    (fp_text reference "C1" (at 0 -1.16 90) (layer "F.SilkS")
+        (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp 49779c79-5be5-4c3d-a87a-cd695f4280ac)
+    )
+    (fp_text value "100nF" (at 0 1.16 90) (layer "F.Fab")
+        (effects (font (size 1 1) (thickness 0.15)))
+      (tstamp f9a9f92c-c124-40e8-82c7-356717cb9cc7)
+    )
+    (fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
+        (effects (font (size 0.25 0.25) (thickness 0.04)))
+      (tstamp 1d1cc735-a677-485c-a0a9-82902dfc3638)
+    )
+    (fp_line (start -0.107836 -0.36) (end 0.107836 -0.36)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 084ab520-9179-401d-8a27-d95139728704))
+    (fp_line (start -0.107836 0.36) (end 0.107836 0.36)
+      (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 1a4641ff-3a92-472f-9215-e25d22ab2de6))
+    (fp_line (start -0.91 -0.46) (end 0.91 -0.46)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b5e2040c-2f99-4f0a-901d-eff17ecf5463))
+    (fp_line (start -0.91 0.46) (end -0.91 -0.46)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 1b5158ab-d16d-4cca-90c2-5f66d1874324))
+    (fp_line (start 0.91 -0.46) (end 0.91 0.46)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp dea54842-50ad-4fa0-bb42-2421d52dfa33))
+    (fp_line (start 0.91 0.46) (end -0.91 0.46)
+      (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp e6edc198-9cb2-4bd3-81e6-d46378c71673))
+    (fp_line (start -0.5 -0.25) (end 0.5 -0.25)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 7755ab06-993f-409e-a5e9-349832b9ffac))
+    (fp_line (start -0.5 0.25) (end -0.5 -0.25)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp dd63c8a3-5dee-42c9-aeeb-848e93e9b935))
+    (fp_line (start 0.5 -0.25) (end 0.5 0.25)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 0510c69f-45c0-4a4c-9149-0f09a081442b))
+    (fp_line (start 0.5 0.25) (end -0.5 0.25)
+      (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 9207a129-7410-4151-a18c-96e7ac5ee529))
+    (pad "1" smd roundrect (at -0.48 0 270) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+      (net 1 "HelloWorld-vcc_5v") (tstamp 90574307-7725-41c5-bb29-62c1e525240f))
+    (pad "2" smd roundrect (at 0.48 0 270) (size 0.56 0.62) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+      (net 2 "HelloWorld-gnd") (tstamp 55316ba4-1ab2-4938-abd4-aae432b75b7f))
+    (model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl"
+      (offset (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_rect (start 119.38 73.66) (end 170.18 121.92)
+    (stroke (width 0.2) (type default)) (fill none) (layer "Edge.Cuts") (tstamp 124ae6a5-3597-4fb4-b4db-99c47e66868e))
+
+  (segment (start 137.744156 90.17) (end 133.991711 93.922445) (width 0.25) (layer "F.Cu") (net 1) (tstamp 2cef6485-b350-4d3f-9148-03a50b3a4f7b))
+  (segment (start 133.991711 93.922445) (end 133.991711 93.930054) (width 0.25) (layer "F.Cu") (net 1) (tstamp 7d78c8ed-d8df-45c3-a118-86cba7172d02))
+  (segment (start 138.43 90.17) (end 137.744156 90.17) (width 0.25) (layer "F.Cu") (net 1) (tstamp ec6940f2-d495-4a8e-8cf0-82f2b3b1bece))
+  (segment (start 136.891657 97.79) (end 133.991711 94.890054) (width 0.25) (layer "F.Cu") (net 2) (tstamp 165d3670-dba7-4575-adc2-d1dd17785954))
+  (segment (start 138.43 97.79) (end 136.891657 97.79) (width 0.25) (layer "F.Cu") (net 2) (tstamp 23d59967-65f9-4109-a278-1c25812ffef1))
+
+)

elec/layout/atopile-project-template.kicad_pro

@@ -0,0 +1,231 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.09999999999999999,
+        "copper_line_width": 0.19999999999999998,
+        "copper_text_italic": false,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "copper_text_upright": false,
+        "courtyard_line_width": 0.049999999999999996,
+        "dimension_precision": 4,
+        "dimension_units": 3,
+        "dimensions": {
+          "arrow_length": 1270000,
+          "extension_offset": 500000,
+          "keep_text_aligned": true,
+          "suppress_zeroes": false,
+          "text_position": 0,
+          "units_format": 1
+        },
+        "fab_line_width": 0.09999999999999999,
+        "fab_text_italic": false,
+        "fab_text_size_h": 1.0,
+        "fab_text_size_v": 1.0,
+        "fab_text_thickness": 0.15,
+        "fab_text_upright": false,
+        "other_line_width": 0.15,
+        "other_text_italic": false,
+        "other_text_size_h": 1.0,
+        "other_text_size_v": 1.0,
+        "other_text_thickness": 0.15,
+        "other_text_upright": false,
+        "pads": {
+          "drill": 0.762,
+          "height": 1.524,
+          "width": 1.524
+        },
+        "silk_line_width": 0.15,
+        "silk_text_italic": false,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15,
+        "silk_text_upright": false,
+        "zones": {
+          "min_clearance": 0.5
+        }
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "meta": {
+        "version": 2
+      },
+      "rule_severities": {
+        "annular_width": "error",
+        "clearance": "error",
+        "connection_width": "warning",
+        "copper_edge_clearance": "error",
+        "copper_sliver": "warning",
+        "courtyards_overlap": "error",
+        "diff_pair_gap_out_of_range": "error",
+        "diff_pair_uncoupled_length_too_long": "error",
+        "drill_out_of_range": "error",
+        "duplicate_footprints": "warning",
+        "extra_footprint": "warning",
+        "footprint": "error",
+        "footprint_type_mismatch": "ignore",
+        "hole_clearance": "error",
+        "hole_near_hole": "error",
+        "invalid_outline": "error",
+        "isolated_copper": "warning",
+        "item_on_disabled_layer": "error",
+        "items_not_allowed": "error",
+        "length_out_of_range": "error",
+        "lib_footprint_issues": "warning",
+        "lib_footprint_mismatch": "warning",
+        "malformed_courtyard": "error",
+        "microvia_drill_out_of_range": "error",
+        "missing_courtyard": "ignore",
+        "missing_footprint": "warning",
+        "net_conflict": "warning",
+        "npth_inside_courtyard": "ignore",
+        "padstack": "warning",
+        "pth_inside_courtyard": "ignore",
+        "shorting_items": "error",
+        "silk_edge_clearance": "warning",
+        "silk_over_copper": "warning",
+        "silk_overlap": "warning",
+        "skew_out_of_range": "error",
+        "solder_mask_bridge": "error",
+        "starved_thermal": "error",
+        "text_height": "warning",
+        "text_thickness": "warning",
+        "through_hole_pad_without_hole": "error",
+        "too_many_vias": "error",
+        "track_dangling": "warning",
+        "track_width": "error",
+        "tracks_crossing": "error",
+        "unconnected_items": "error",
+        "unresolved_variable": "error",
+        "via_dangling": "warning",
+        "zones_intersect": "error"
+      },
+      "rules": {
+        "max_error": 0.005,
+        "min_clearance": 0.0,
+        "min_connection": 0.0,
+        "min_copper_edge_clearance": 0.0,
+        "min_hole_clearance": 0.25,
+        "min_hole_to_hole": 0.25,
+        "min_microvia_diameter": 0.19999999999999998,
+        "min_microvia_drill": 0.09999999999999999,
+        "min_resolved_spokes": 2,
+        "min_silk_clearance": 0.0,
+        "min_text_height": 0.7999999999999999,
+        "min_text_thickness": 0.08,
+        "min_through_hole_diameter": 0.3,
+        "min_track_width": 0.0,
+        "min_via_annular_width": 0.09999999999999999,
+        "min_via_diameter": 0.5,
+        "solder_mask_clearance": 0.0,
+        "solder_mask_min_width": 0.0,
+        "solder_mask_to_copper_clearance": 0.0,
+        "use_height_for_length_calcs": true
+      },
+      "teardrop_options": [
+        {
+          "td_allow_use_two_tracks": true,
+          "td_curve_segcount": 5,
+          "td_on_pad_in_zone": false,
+          "td_onpadsmd": true,
+          "td_onroundshapesonly": false,
+          "td_ontrackend": false,
+          "td_onviapad": true
+        }
+      ],
+      "teardrop_parameters": [
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_round_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_rect_shape",
+          "td_width_to_size_filter_ratio": 0.9
+        },
+        {
+          "td_curve_segcount": 0,
+          "td_height_ratio": 1.0,
+          "td_length_ratio": 0.5,
+          "td_maxheight": 2.0,
+          "td_maxlen": 1.0,
+          "td_target_name": "td_track_end",
+          "td_width_to_size_filter_ratio": 0.9
+        }
+      ],
+      "track_widths": [],
+      "via_dimensions": [],
+      "zones_allow_external_fillets": false
+    },
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "atopile-project-template.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 3
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "../../build/default/template_code.net",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
+    "legacy_lib_dir": "",
+    "legacy_lib_list": []
+  },
+  "sheets": [],
+  "text_variables": {}
+}

elec/layout/atopile-project-template.kicad_sch

@@ -0,0 +1,5 @@
+(kicad_sch (version 20230121) (generator eeschema)
+  (paper "A4")
+  (lib_symbols)
+  (symbol_instances)
+)

elec/layout/fp-lib-table

@@ -0,0 +1,4 @@
+(fp_lib_table
+  (version 7)
+  (lib (name "lib")(type "KiCad")(uri "${KIPRJMOD}/../lib/lib.pretty")(options "")(descr ""))
+)

elec/lib/lib.kicad_sym

@@ -0,0 +1,105 @@
+(kicad_symbol_lib
+  (version 20211014)
+  (generator https://github.com/uPesy/easyeda2kicad.py)
+  (symbol "LM555N"
+    (in_bom yes)
+    (on_board yes)
+    (property
+      "Reference"
+      "U"
+      (id 0)
+      (at 0 8.89 0)
+      (effects (font (size 1.27 1.27) ) )
+    )
+    (property
+      "Value"
+      "LM555N"
+      (id 1)
+      (at 0 -8.89 0)
+      (effects (font (size 1.27 1.27) ) )
+    )
+    (property
+      "Footprint"
+      "lib:DIP-8_L9.7-W6.4-P2.54-LS7.6-BL"
+      (id 2)
+      (at 0 -11.43 0)
+      (effects (font (size 1.27 1.27) ) hide)
+    )
+    (property
+      "Datasheet"
+      "https://lcsc.com/product-detail/Clock-Timing-Application-Specific_HGSEMI-LM555N_C725327.html"
+      (id 3)
+      (at 0 -13.97 0)
+      (effects (font (size 1.27 1.27) ) hide)
+    )
+    (property
+      "LCSC Part"
+      "C725327"
+      (id 5)
+      (at 0 -16.51 0)
+      (effects (font (size 1.27 1.27) ) hide)
+    )
+    (symbol "LM555N_0_1"
+      (rectangle
+        (start -20.32 6.35)
+        (end 20.32 -6.35)
+        (stroke (width 0) (type default) (color 0 0 0 0))
+        (fill (type background))
+      )
+      (circle
+        (center -19.05 5.08)
+        (radius 0.38)
+        (stroke (width 0) (type default) (color 0 0 0 0))
+        (fill (type none))
+      )
+      (pin unspecified line
+        (at -22.86 3.81 0)
+        (length 2.54)
+        (name "GND" (effects (font (size 1.27 1.27))))
+        (number "1" (effects (font (size 1.27 1.27))))
+      )
+      (pin unspecified line
+        (at -22.86 1.27 0)
+        (length 2.54)
+        (name "TRIGGER" (effects (font (size 1.27 1.27))))
+        (number "2" (effects (font (size 1.27 1.27))))
+      )
+      (pin unspecified line
+        (at -22.86 -1.27 0)
+        (length 2.54)
+        (name "OUTPUT" (effects (font (size 1.27 1.27))))
+        (number "3" (effects (font (size 1.27 1.27))))
+      )
+      (pin unspecified line
+        (at -22.86 -3.81 0)
+        (length 2.54)
+        (name "RESET" (effects (font (size 1.27 1.27))))
+        (number "4" (effects (font (size 1.27 1.27))))
+      )
+      (pin unspecified line
+        (at 22.86 -3.81 180)
+        (length 2.54)
+        (name "CONTROLVOLTAGE" (effects (font (size 1.27 1.27))))
+        (number "5" (effects (font (size 1.27 1.27))))
+      )
+      (pin unspecified line
+        (at 22.86 -1.27 180)
+        (length 2.54)
+        (name "THRESHOLD" (effects (font (size 1.27 1.27))))
+        (number "6" (effects (font (size 1.27 1.27))))
+      )
+      (pin unspecified line
+        (at 22.86 1.27 180)
+        (length 2.54)
+        (name "DISCHARGE" (effects (font (size 1.27 1.27))))
+        (number "7" (effects (font (size 1.27 1.27))))
+      )
+      (pin unspecified line
+        (at 22.86 3.81 180)
+        (length 2.54)
+        (name "VCC" (effects (font (size 1.27 1.27))))
+        (number "8" (effects (font (size 1.27 1.27))))
+      )
+    )
+  )
+)

elec/lib/lib.pretty/DIP-8_L9.7-W6.4-P2.54-LS7.6-BL.kicad_mod

@@ -0,0 +1,33 @@
+(module easyeda2kicad:DIP-8_L9.7-W6.4-P2.54-LS7.6-BL (layer F.Cu) (tedit 5DC5F6A4)
+	(attr smd)
+	(fp_text reference REF** (at 0 -7.8100000000000005) (layer F.SilkS)
+		(effects (font (size 1 1) (thickness 0.15)))
+	)
+	(fp_text value DIP-8_L9.7-W6.4-P2.54-LS7.6-BL (at 0 7.8100000000000005) (layer F.Fab)
+		(effects (font (size 1 1) (thickness 0.15)))
+	)
+	(fp_text user %R (at 0 0) (layer F.Fab)
+		(effects (font (size 1 1) (thickness 0.15)))
+	)
+	(fp_line (start -5.08 2.54) (end 5.08 2.54) (layer F.SilkS) (width 0.25))
+	(fp_line (start -5.08 -2.53) (end 5.08 -2.53) (layer F.SilkS) (width 0.25))
+	(fp_line (start 5.08 2.54) (end 5.08 -2.53) (layer F.SilkS) (width 0.25))
+	(fp_line (start -5.08 2.54) (end -5.08 0.77) (layer F.SilkS) (width 0.25))
+	(fp_line (start -5.08 -0.76) (end -5.08 -2.53) (layer F.SilkS) (width 0.25))
+	(pad 1 thru_hole rect (at -3.81 3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(pad 2 thru_hole circle (at -1.27 3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(pad 3 thru_hole circle (at 1.27 3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(pad 4 thru_hole circle (at 3.81 3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(pad 5 thru_hole circle (at 3.81 -3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(pad 6 thru_hole circle (at 1.27 -3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(pad 7 thru_hole circle (at -1.27 -3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(pad 8 thru_hole circle (at -3.81 -3.81 0.00) (size 1.80 1.80) (layers *.Cu *.Mask)(drill 0.9999979999999999))
+	(fp_circle (center -4.83 3.94) (end -4.80 3.94) (layer F.Fab) (width 0.06))
+	(fp_circle (center -3.94 4.45) (end -3.64 4.45) (layer Cmts.User) (width 0.60))
+	(fp_arc (start -5.08 0.00) (end -5.08 0.77) (angle -359.00) (layer F.SilkS) (width 0.25))
+	(model "./lib/lib.3dshapes/DIP-8_L9.8-W6.6-H3.5-LS7.62-P2.54.wrl"
+		(offset (xyz 0.000 -0.000 3.000))
+		(scale (xyz 1 1 1))
+		(rotate (xyz 0 0 0))
+	)
+)

elec/src/ato.yaml

@@ -0,0 +1,11 @@
+ato-version: ^0.0.18
+paths:
+  build: ../../build/
+builds:
+  default:
+    root-file: template_code.ato
+    root-node: template_code.ato:HelloWorld
+    targets:
+      - designators
+      - netlist-kicad6
+      - bom-jlcpcb

elec/src/default-bom-jlcpcb.yaml

@@ -0,0 +1,12 @@
+by-spec:
+- instance_of: template_code.ato:Timer555Dip8
+  footprint: lib:DIP-8_L9.7-W6.4-P2.54-LS7.6-BL
+  jlcpcb: C725327
+- instance_of: std/resistor.ato:Resistor
+  footprint: Resistor_SMD:R_0402_1005Metric
+  value: 10k
+  jlcpcb: C216802
+- instance_of: std/capacitor.ato:Capacitor
+  footprint: Capacitor_SMD:C_0402_1005Metric
+  value: 100nF
+  jlcpcb: C307331

elec/src/default-designators.yaml

@@ -0,0 +1,3 @@
+timer: U1
+bypass_cap: C1
+resistor: R1

elec/src/template_code.ato

@@ -0,0 +1,51 @@
+# this is template code for an ato project
+# for more complex examples, head over to:
+# https://gitlab.atopile.io/atopile/servo-drive
+
+# we can start off by importing some standard components
+import Capacitor from "std/capacitor.ato"
+
+# we can then import project specific components or modules
+# a module is a collection of components that are used together
+# you can also create components from jlc using the easyeday2ato command
+# for more information, see the ato documentation here: http://docs.atopile.io/#adding-footprints-to-your-project
+
+# if you cannot find a component you need, you can always define it yourself!
+component Timer555Dip8:
+    signal gnd ~ pin p1
+    signal trigger ~ pin p2
+    signal output ~ pin p3
+    signal reset ~ pin p4
+    signal ctrl_v ~ pin p5
+    signal threshold ~ pin p6
+    signal discharge ~ pin p7
+    signal vcc ~ pin p8
+
+    footprint = "lib:DIP-8_L9.7-W6.4-P2.54-LS7.6-BL"
+
+# this is your top level module, as defined in the ato.yaml file
+module HelloWorld:
+    signal vcc_5v
+    signal gnd
+
+    # this is a component instantiation
+    timer = new Timer555Dip8
+
+    timer.vcc ~ vcc_5v
+    timer.gnd ~ gnd
+
+    # this is a capacitor instantiation
+    bypass_cap = new Capacitor
+    # we can set the value of the capacitor
+    bypass_cap.value = "100nF"
+    # we can also set the footprint of the capacitor
+    bypass_cap.footprint = "Capacitor_SMD:C_0402_1005Metric"
+
+    # we can connect the capacitor to the vcc and gnd signals
+    bypass_cap.p1 ~ vcc_5v
+    bypass_cap.p2 ~ gnd
+
+# thats it! run ato build from the src directory to generate the kicad netlist
+# help: http://docs.atopile.io/#building-the-netlist
+# if you have added new components, you may need to run ato resolve then fill in the jlcpcb part numbers in default-bom-jlcpcb.yaml
+# to get netlist into kicad, follow these steps: http://docs.atopile.io/#importing-to-kicad

metadata/pos-header

@@ -0,0 +1 @@
+Designator,Value,Package,Mid X,Mid Y,Rotation,Layer