3.2 KiB
3.2 KiB
| 1 | I2C0_CONSET | 2 | 1 | AA | Assert acknowledge flag | 0 | rw |
|---|---|---|---|---|---|---|---|
| 2 | I2C0_CONSET | 3 | 1 | SI | I2C interrupt flag | 0 | rw |
| 3 | I2C0_CONSET | 4 | 1 | STO | STOP flag | 0 | rw |
| 4 | I2C0_CONSET | 5 | 1 | STA | START flag | 0 | rw |
| 5 | I2C0_CONSET | 6 | 1 | I2EN | I2C interface enable | 0 | rw |
| 6 | I2C1_CONSET | 2 | 1 | AA | Assert acknowledge flag | 0 | rw |
| 7 | I2C1_CONSET | 3 | 1 | SI | I2C interrupt flag | 0 | rw |
| 8 | I2C1_CONSET | 4 | 1 | STO | STOP flag | 0 | rw |
| 9 | I2C1_CONSET | 5 | 1 | STA | START flag | 0 | rw |
| 10 | I2C1_CONSET | 6 | 1 | I2EN | I2C interface enable | 0 | rw |
| 11 | I2C0_STAT | 3 | 5 | STATUS | These bits give the actual status information about the I2C interface | 0x1f | r |
| 12 | I2C1_STAT | 3 | 5 | STATUS | These bits give the actual status information about the I2C interface | 0x1f | r |
| 13 | I2C0_DAT | 0 | 8 | DATA | This register holds data values that have been received or are to be transmitted | 0 | rw |
| 14 | I2C1_DAT | 0 | 8 | DATA | This register holds data values that have been received or are to be transmitted | 0 | rw |
| 15 | I2C0_ADR0 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 16 | I2C0_ADR0 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 17 | I2C1_ADR0 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 18 | I2C1_ADR0 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 19 | I2C0_SCLH | 0 | 16 | SCLH | Count for SCL HIGH time period selection | 0x0004 | rw |
| 20 | I2C1_SCLH | 0 | 16 | SCLH | Count for SCL HIGH time period selection | 0x0004 | rw |
| 21 | I2C0_SCLL | 0 | 16 | SCLL | Count for SCL LOW time period selection | 0x0004 | rw |
| 22 | I2C1_SCLL | 0 | 16 | SCLL | Count for SCL LOW time period selection | 0x0004 | rw |
| 23 | I2C0_CONCLR | 2 | 1 | AAC | Assert acknowledge Clear bit | 0 | w |
| 24 | I2C0_CONCLR | 3 | 1 | SIC | I2C interrupt Clear bit | 0 | w |
| 25 | I2C0_CONCLR | 5 | 1 | STAC | START flag Clear bit | 0 | w |
| 26 | I2C0_CONCLR | 6 | 1 | I2ENC | I2C interface Disable bit | 0 | w |
| 27 | I2C1_CONCLR | 2 | 1 | AAC | Assert acknowledge Clear bit | 0 | w |
| 28 | I2C1_CONCLR | 3 | 1 | SIC | I2C interrupt Clear bit | 0 | w |
| 29 | I2C1_CONCLR | 5 | 1 | STAC | START flag Clear bit | 0 | w |
| 30 | I2C1_CONCLR | 6 | 1 | I2ENC | I2C interface Disable bit | 0 | w |
| 31 | I2C0_MMCTRL | 0 | 1 | MM_ENA | Monitor mode enable | 0 | rw |
| 32 | I2C0_MMCTRL | 1 | 1 | ENA_SCL | SCL output enable | 0 | rw |
| 33 | I2C0_MMCTRL | 2 | 1 | MATCH_ALL | Select interrupt register match | 0 | rw |
| 34 | I2C1_MMCTRL | 0 | 1 | MM_ENA | Monitor mode enable | 0 | rw |
| 35 | I2C1_MMCTRL | 1 | 1 | ENA_SCL | SCL output enable | 0 | rw |
| 36 | I2C1_MMCTRL | 2 | 1 | MATCH_ALL | Select interrupt register match | 0 | rw |
| 37 | I2C0_ADR1 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 38 | I2C0_ADR1 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 39 | I2C1_ADR1 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 40 | I2C1_ADR1 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 41 | I2C0_ADR2 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 42 | I2C0_ADR2 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 43 | I2C1_ADR2 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 44 | I2C1_ADR2 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 45 | I2C0_ADR3 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 46 | I2C0_ADR3 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 47 | I2C1_ADR3 | 0 | 1 | GC | General Call enable bit | 0 | rw |
| 48 | I2C1_ADR3 | 1 | 7 | ADDRESS | The I2C device address for slave mode | 0 | rw |
| 49 | I2C0_DATA_BUFFER | 0 | 8 | DATA | This register holds contents of the 8 MSBs of the DAT shift register | 0 | r |
| 50 | I2C1_DATA_BUFFER | 0 | 8 | DATA | This register holds contents of the 8 MSBs of the DAT shift register | 0 | r |
| 51 | I2C0_MASK0 | 1 | 7 | MASK | Mask bits | 0 | rw |
| 52 | I2C1_MASK0 | 1 | 7 | MASK | Mask bits | 0 | rw |
| 53 | I2C0_MASK1 | 1 | 7 | MASK | Mask bits | 0 | rw |
| 54 | I2C1_MASK1 | 1 | 7 | MASK | Mask bits | 0 | rw |
| 55 | I2C0_MASK2 | 1 | 7 | MASK | Mask bits | 0 | rw |
| 56 | I2C1_MASK2 | 1 | 7 | MASK | Mask bits | 0 | rw |
| 57 | I2C0_MASK3 | 1 | 7 | MASK | Mask bits | 0 | rw |
| 58 | I2C1_MASK3 | 1 | 7 | MASK | Mask bits | 0 | rw |