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+/*
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+ * Copyright (C) 2013 Oskar Andero <oskar.andero@gmail.com>
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+ * Copyright (C) 2014 Rose Technology
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+ * Allan Bendorff Jensen <abj@rosetechnology.dk>
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+ * Soren Andersen <san@rosetechnology.dk>
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+ *
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+ * Driver for following ADC chips from Microchip Technology's:
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+ * 10 Bit converter
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+ * MCP3001
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+ * MCP3002
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+ * MCP3004
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+ * MCP3008
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+ * ------------
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+ * 12 bit converter
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+ * MCP3201
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+ * MCP3202
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+ * MCP3204
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+ * MCP3208
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+ * ------------
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+ *
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+ * Datasheet can be found here:
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+ * http://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001
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+ * http://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf mcp3002
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+ * http://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf mcp3004/08
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+ * http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf mcp3201
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+ * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202
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+ * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08
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+ * http://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/err.h>
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+#include <linux/delay.h>
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+#include <linux/spi/spi.h>
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+#include <linux/module.h>
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+#include <linux/iio/iio.h>
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+#include <linux/regulator/consumer.h>
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+
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+enum {
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+ mcp3001,
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+ mcp3002,
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+ mcp3004,
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+ mcp3008,
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+ mcp3201,
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+ mcp3202,
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+ mcp3204,
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+ mcp3208,
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+ mcp3301,
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+};
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+
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+struct mcp320x_chip_info {
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+ const struct iio_chan_spec *channels;
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+ unsigned int num_channels;
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+ unsigned int resolution;
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+};
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+
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+struct mcp320x {
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+ struct spi_device *spi;
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+ struct spi_message msg;
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+ struct spi_transfer transfer[2];
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+
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+ struct regulator *reg;
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+ struct mutex lock;
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+ const struct mcp320x_chip_info *chip_info;
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+
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+ u8 tx_buf ____cacheline_aligned;
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+ u8 rx_buf[2];
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+};
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+
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+static int mcp320x_channel_to_tx_data(int device_index,
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+ const unsigned int channel, bool differential)
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+{
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+ int start_bit = 1;
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+
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+ switch (device_index) {
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+ case mcp3001:
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+ case mcp3201:
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+ case mcp3301:
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+ return 0;
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+ case mcp3002:
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+ case mcp3202:
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+ return ((start_bit << 4) | (!differential << 3) |
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+ (channel << 2));
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+ case mcp3004:
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+ case mcp3204:
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+ case mcp3008:
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+ case mcp3208:
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+ return ((start_bit << 6) | (!differential << 5) |
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+ (channel << 2));
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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+static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
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+ bool differential, int device_index)
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+{
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+ int ret;
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+
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+ adc->rx_buf[0] = 0;
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+ adc->rx_buf[1] = 0;
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+ adc->tx_buf = mcp320x_channel_to_tx_data(device_index,
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+ channel, differential);
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+
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+ if (device_index != mcp3001 && device_index != mcp3201 && device_index != mcp3301) {
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+ ret = spi_sync(adc->spi, &adc->msg);
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+ if (ret < 0)
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+ return ret;
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+ } else {
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+ ret = spi_read(adc->spi, &adc->rx_buf, sizeof(adc->rx_buf));
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ switch (device_index) {
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+ case mcp3001:
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+ return (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
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+ case mcp3002:
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+ case mcp3004:
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+ case mcp3008:
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+ return (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
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+ case mcp3201:
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+ return (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
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+ case mcp3202:
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+ case mcp3204:
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+ case mcp3208:
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+ return (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
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+ case mcp3301:
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+ return sign_extend32((adc->rx_buf[0] & 0x1f) << 8 | adc->rx_buf[1], 12);
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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+static int mcp320x_read_raw(struct iio_dev *indio_dev,
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+ struct iio_chan_spec const *channel, int *val,
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+ int *val2, long mask)
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+{
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+ struct mcp320x *adc = iio_priv(indio_dev);
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+ int ret = -EINVAL;
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+ int device_index = 0;
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+
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+ mutex_lock(&adc->lock);
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+
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+ device_index = spi_get_device_id(adc->spi)->driver_data;
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+
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+ switch (mask) {
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+ case IIO_CHAN_INFO_RAW:
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+ ret = mcp320x_adc_conversion(adc, channel->address,
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+ channel->differential, device_index);
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+
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+ if (ret < 0)
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+ goto out;
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+
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+ *val = ret;
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+ ret = IIO_VAL_INT;
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+ break;
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+
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+ case IIO_CHAN_INFO_SCALE:
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+ ret = regulator_get_voltage(adc->reg);
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+ if (ret < 0)
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+ goto out;
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+
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+ /* convert regulator output voltage to mV */
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+ *val = ret / 1000;
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+ *val2 = adc->chip_info->resolution;
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+ ret = IIO_VAL_FRACTIONAL_LOG2;
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+ break;
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+ }
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+
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+out:
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+ mutex_unlock(&adc->lock);
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+
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+ return ret;
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+}
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+
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+#define MCP320X_VOLTAGE_CHANNEL(num) \
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+ { \
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+ .type = IIO_VOLTAGE, \
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+ .indexed = 1, \
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+ .channel = (num), \
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+ .address = (num), \
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+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
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+ }
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+
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+#define MCP320X_VOLTAGE_CHANNEL_DIFF(num) \
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+ { \
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+ .type = IIO_VOLTAGE, \
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+ .indexed = 1, \
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+ .channel = (num * 2), \
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+ .channel2 = (num * 2 + 1), \
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+ .address = (num * 2), \
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+ .differential = 1, \
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+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
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+ }
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+
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+static const struct iio_chan_spec mcp3201_channels[] = {
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(0),
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+};
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+
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+static const struct iio_chan_spec mcp3202_channels[] = {
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+ MCP320X_VOLTAGE_CHANNEL(0),
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+ MCP320X_VOLTAGE_CHANNEL(1),
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(0),
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+};
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+
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+static const struct iio_chan_spec mcp3204_channels[] = {
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+ MCP320X_VOLTAGE_CHANNEL(0),
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+ MCP320X_VOLTAGE_CHANNEL(1),
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+ MCP320X_VOLTAGE_CHANNEL(2),
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+ MCP320X_VOLTAGE_CHANNEL(3),
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(0),
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(1),
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+};
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+
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+static const struct iio_chan_spec mcp3208_channels[] = {
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+ MCP320X_VOLTAGE_CHANNEL(0),
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+ MCP320X_VOLTAGE_CHANNEL(1),
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+ MCP320X_VOLTAGE_CHANNEL(2),
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+ MCP320X_VOLTAGE_CHANNEL(3),
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+ MCP320X_VOLTAGE_CHANNEL(4),
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+ MCP320X_VOLTAGE_CHANNEL(5),
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+ MCP320X_VOLTAGE_CHANNEL(6),
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+ MCP320X_VOLTAGE_CHANNEL(7),
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(0),
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(1),
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(2),
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+ MCP320X_VOLTAGE_CHANNEL_DIFF(3),
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+};
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+
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+static const struct iio_info mcp320x_info = {
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+ .read_raw = mcp320x_read_raw,
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+ .driver_module = THIS_MODULE,
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+};
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+
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+static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
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+ [mcp3001] = {
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+ .channels = mcp3201_channels,
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+ .num_channels = ARRAY_SIZE(mcp3201_channels),
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+ .resolution = 10
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+ },
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+ [mcp3002] = {
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+ .channels = mcp3202_channels,
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+ .num_channels = ARRAY_SIZE(mcp3202_channels),
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+ .resolution = 10
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+ },
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+ [mcp3004] = {
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+ .channels = mcp3204_channels,
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+ .num_channels = ARRAY_SIZE(mcp3204_channels),
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+ .resolution = 10
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+ },
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+ [mcp3008] = {
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+ .channels = mcp3208_channels,
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+ .num_channels = ARRAY_SIZE(mcp3208_channels),
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+ .resolution = 10
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+ },
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+ [mcp3201] = {
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+ .channels = mcp3201_channels,
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+ .num_channels = ARRAY_SIZE(mcp3201_channels),
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+ .resolution = 12
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+ },
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+ [mcp3202] = {
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+ .channels = mcp3202_channels,
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+ .num_channels = ARRAY_SIZE(mcp3202_channels),
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+ .resolution = 12
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+ },
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+ [mcp3204] = {
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+ .channels = mcp3204_channels,
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+ .num_channels = ARRAY_SIZE(mcp3204_channels),
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+ .resolution = 12
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+ },
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+ [mcp3208] = {
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+ .channels = mcp3208_channels,
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+ .num_channels = ARRAY_SIZE(mcp3208_channels),
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+ .resolution = 12
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+ },
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+ [mcp3301] = {
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+ .channels = mcp3201_channels,
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+ .num_channels = ARRAY_SIZE(mcp3201_channels),
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+ .resolution = 13
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+ },
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+};
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+
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+static int mcp320x_probe(struct spi_device *spi)
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+{
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+ struct iio_dev *indio_dev;
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+ struct mcp320x *adc;
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+ const struct mcp320x_chip_info *chip_info;
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+ int ret;
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+
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+ indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
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+ if (!indio_dev)
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+ return -ENOMEM;
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+
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+ adc = iio_priv(indio_dev);
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+ adc->spi = spi;
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+
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+ indio_dev->dev.parent = &spi->dev;
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+ indio_dev->name = spi_get_device_id(spi)->name;
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+ indio_dev->modes = INDIO_DIRECT_MODE;
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+ indio_dev->info = &mcp320x_info;
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+
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+ chip_info = &mcp320x_chip_infos[spi_get_device_id(spi)->driver_data];
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+ indio_dev->channels = chip_info->channels;
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+ indio_dev->num_channels = chip_info->num_channels;
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+
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+ adc->chip_info = chip_info;
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+
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+ adc->transfer[0].tx_buf = &adc->tx_buf;
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+ adc->transfer[0].len = sizeof(adc->tx_buf);
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+ adc->transfer[1].rx_buf = adc->rx_buf;
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+ adc->transfer[1].len = sizeof(adc->rx_buf);
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+
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+ spi_message_init_with_transfers(&adc->msg, adc->transfer,
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+ ARRAY_SIZE(adc->transfer));
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+
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+ adc->reg = devm_regulator_get(&spi->dev, "vref");
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+ if (IS_ERR(adc->reg))
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+ return PTR_ERR(adc->reg);
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+
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+ ret = regulator_enable(adc->reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ mutex_init(&adc->lock);
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+
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+ ret = iio_device_register(indio_dev);
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+ if (ret < 0)
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+ goto reg_disable;
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+
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+ return 0;
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+
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+reg_disable:
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+ regulator_disable(adc->reg);
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+
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+ return ret;
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+}
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+
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+static int mcp320x_remove(struct spi_device *spi)
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+{
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+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
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+ struct mcp320x *adc = iio_priv(indio_dev);
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+
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+ iio_device_unregister(indio_dev);
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+ regulator_disable(adc->reg);
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+
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+ return 0;
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+}
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+
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+#if defined(CONFIG_OF)
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+static const struct of_device_id mcp320x_dt_ids[] = {
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+ {
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+ .compatible = "mcp3001",
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+ .data = &mcp320x_chip_infos[mcp3001],
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+ }, {
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+ .compatible = "mcp3002",
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+ .data = &mcp320x_chip_infos[mcp3002],
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+ }, {
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+ .compatible = "mcp3004",
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+ .data = &mcp320x_chip_infos[mcp3004],
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+ }, {
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+ .compatible = "mcp3008",
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+ .data = &mcp320x_chip_infos[mcp3008],
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+ }, {
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+ .compatible = "mcp3201",
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+ .data = &mcp320x_chip_infos[mcp3201],
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+ }, {
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+ .compatible = "mcp3202",
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+ .data = &mcp320x_chip_infos[mcp3202],
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+ }, {
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+ .compatible = "mcp3204",
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+ .data = &mcp320x_chip_infos[mcp3204],
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+ }, {
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+ .compatible = "mcp3208",
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+ .data = &mcp320x_chip_infos[mcp3208],
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+ }, {
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+ .compatible = "mcp3301",
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+ .data = &mcp320x_chip_infos[mcp3301],
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+ }, {
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+ }
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+};
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+MODULE_DEVICE_TABLE(of, mcp320x_dt_ids);
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+#endif
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+
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+static const struct spi_device_id mcp320x_id[] = {
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+ { "mcp3001", mcp3001 },
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+ { "mcp3002", mcp3002 },
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+ { "mcp3004", mcp3004 },
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+ { "mcp3008", mcp3008 },
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+ { "mcp3201", mcp3201 },
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+ { "mcp3202", mcp3202 },
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+ { "mcp3204", mcp3204 },
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+ { "mcp3208", mcp3208 },
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|
|
+ { "mcp3301", mcp3301 },
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|
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+ { }
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|
|
+};
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|
|
+MODULE_DEVICE_TABLE(spi, mcp320x_id);
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|
|
+
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|
|
+static struct spi_driver mcp320x_driver = {
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|
|
+ .driver = {
|
|
|
+ .name = "mcp320x",
|
|
|
+ .of_match_table = of_match_ptr(mcp320x_dt_ids),
|
|
|
+ },
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|
|
+ .probe = mcp320x_probe,
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|
|
+ .remove = mcp320x_remove,
|
|
|
+ .id_table = mcp320x_id,
|
|
|
+};
|
|
|
+module_spi_driver(mcp320x_driver);
|
|
|
+
|
|
|
+MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>");
|
|
|
+MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08");
|
|
|
+MODULE_LICENSE("GPL v2");
|